IP Library Granted Patent US 9,907,175
Granted Patent B2
US 9,907,175 · App. 14/771,662 · Granted Feb 27, 2018

Semiconductor device

Inventor: Atsushi Tomohiro (Tokyo, JP)
Assignee: Longitude Semiconductors S.A.R.L.
H05K1/181H01L23/498H01L23/49827H01L24/97H01L25/105H05K1/0203H05K1/111H01L21/561H01L23/3128H01L23/49816H01L24/73H01L2224/16225H01L2224/32225H01L2224/48091H01L2224/48227H01L2224/48228H01L2224/73204H01L2224/73265H01L2224/92247H01L2224/97H01L2225/1023H01L2225/1058H01L2225/1094H01L2924/181H05K2201/10159
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Quick Facts
Patent No.
US 9,907,175
App. No.
14/771,662
Granted
Feb 27, 2018
Kind
B2
Abstract

One semiconductor device includes a wiring substrate, a semiconductor chip, and a sealing body. The wiring substrate includes an insulating base material, a first conductive pattern formed on one surface of the insulating base material, and a second conductive pattern formed on one surface of the insulating base material, connected to the first conductive pattern and having an end face exposed to the side. The semiconductor chip is mounted on the wiring substrate so as to overlap with the first conductive pattern. The sealing body is formed on the wiring substrate so as to cover the semiconductor chip.

Claims (23)

1. A semiconductor device comprising:

a wiring substrate having an insulating base material, a first conductive pattern formed on a first surface of the insulating base material, and a second conductive pattern formed on the first surface of the insulating base material, connected to the first conductive pattern, and exposed to the side at an end face;

a semiconductor chip mounted on the wiring substrate so as to overlie the first conductive pattern; and

a sealing body formed on the wiring substrate so as to cover the semiconductor chip.

2. The semiconductor device as claimed in claim 1 , wherein the wiring substrate has an insulating film formed on the first surface of the insulating base material so as to cover the first conductive pattern and expose the second conductive pattern.

3. The semiconductor device as claimed in claim 1 , wherein a plating layer is disposed on the surface of the second conductive pattern.

4. The semiconductor device as claimed in claim 1 , wherein the first conductive pattern is connected to the second conductive pattern by a connection wiring.

5. The semiconductor device as claimed in claim 1 , wherein the wiring substrate has a connection pad, and the insulating film has an opening located opposite the connection pad; and

the first conductive pattern is connected to the connection pad.

6. A semiconductor device comprising:

a wiring substrate having an insulating base material, and a wiring pattern and a connection pad formed on a first surface of the insulating base material;

a semiconductor chip mounted on the wiring substrate so as to overlie the wiring pattern; and

a sealing body formed on the first surface of the wiring substrate so as to cover the semiconductor chip;

wherein a portion of the wiring pattern comprises a first conductive pattern connected to the connection pad, and a second conductive pattern connected to the first conductive pattern and exposed to the side at an end face.

7. A semiconductor device comprising:

an upper package having:

a wiring substrate having an insulating base material, a first conductive pattern formed on a first surface of the insulating base material, and a second conductive pattern formed on the first surface of the insulating base material, connected to the first conductive pattern, and exposed to the side at an end face;

a semiconductor chip mounted on the wiring substrate so as to overlie the first conductive pattern;

a sealing body formed on the wiring substrate so as to cover the semiconductor chip; and

metal balls disposed on a second surface of the wiring substrate along each side of the wiring substrate in a region excluding a central region of the wiring substrate; and

a lower package having a wiring substrate comprising an insulating base material, a semiconductor chip mounted on a first surface of the wiring substrate, and metal balls mounted on a second surface of the wiring substrate;

wherein the upper package and the lower package are stacked so that the metal balls of the upper package do not contact the semiconductor chip of the lower package, and contact the wiring substrate of the lower package.

8. The semiconductor device as claimed in claim 7 , wherein connection lands are disposed on the first surface of the wiring substrate of the lower package, and the metal balls of the upper package are connected to the connection lands of the lower package.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2018
From: LONGITUDE SEMICONDUCTOR S.A.R.L.
To: LONGITUDE LICENSING LIMITED
Reel/Frame 046863/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 26, 2017
From: PS4 LUXCO S.A.R.L.
To: PS5 LUXCO S.A.R.L.
Reel/Frame 042586/0772 →
CHANGE OF NAME Recorded May 26, 2017
From: PS5 LUXCO S.A.R.L.
To: LONGITUDE SEMICONDUCTOR S.A.R.L.
Reel/Frame 042589/0346 →
Priority Claims (1)
JP 2013-041598 · Mar 4, 2013 · national
Continuity (1)
Related Publication 20160029491A1 · Jan 28, 2016