Trigate transistor structure with unrecessed field insulator and thinner electrodes over the field insulator

1. An integrated circuit device comprising:

a semiconductor pillar disposed over a device region of a substrate, the semiconductor pillar having a base portion and a fin portion;

a field insulator disposed over a field region of the substrate and adjacent to the base portion of the semiconductor pillar;

a gate electrode coupled to the fin portion of the semiconductor pillar in the device region and disposed over the field insulator in the field region, wherein the gate electrode has a first depth over the device region and a second depth less than the first depth over the field region;

a source electrode coupled to the fin portion of the semiconductor pillar in the device region and disposed over the field insulator in the field region, wherein the source electrode has a third depth over the device region and a fourth depth less than the third depth over the field region; and

a drain electrode coupled to the fin portion of the semiconductor pillar in the device region and disposed over the field insulator in the field region, wherein the drain electrode has a fifth depth over the device region and a sixth depth less than the fifth depth over the field region,

wherein the fin portion of the semiconductor pillar comprises a channel region adjacent to the gate electrode, and a source region and a drain region on opposite sides of the channel region, wherein the source region is adjacent to the source electrode, and wherein the drain region is adjacent to the drain electrode.

2. The integrated circuit device of claim 1 , wherein the field insulator has a top surface at a first height above a surface of the substrate, wherein the fin portion of the semiconductor pillar has a bottom surface at a second height above the surface of the substrate and a top surface at a third height above the surface of the substrate, and the first height is between the second height and the third height.

3. The integrated circuit device of claim 1 , further comprising:

a conformal oxide insulator layer between the base portion of the semiconductor pillar and the field insulator and in contact with the base portion of the semiconductor pillar; and

a conformal nitride insulator layer between the base portion of the semiconductor pillar and the field insulator and in contact with the first conformal insulator layer and the field insulator.

4. The integrated circuit device of claim 1 , further comprising:

a first conformal insulator layer between the base portion of the semiconductor pillar and the field insulator, wherein the first conformal insulator layer is in contact with the base portion of the semiconductor pillar;

a second conformal insulator layer between the base portion of the semiconductor pillar and the field insulator, wherein the second conformal insulator layer is in contact with the first conformal insulator layer and the field insulator; and

a gate dielectric disposed between the gate electrode and the fin portion of the semiconductor pillar, wherein the gate electrode comprises a bulk material and a work function material disposed between the bulk material and the gate dielectric.

5. A microprocessor comprising:

an SRAM cache memory further comprising a transistor including:

a semiconductor pillar disposed over a device region of a substrate, the semiconductor pillar having a base portion and a fin portion;

a field insulator disposed over a field region of the substrate and adjacent to the base portion of the semiconductor pillar;

a gate electrode coupled to the fin portion of the semiconductor pillar in the device region and disposed over the field insulator in the field region, wherein the gate electrode has a first depth over the device region and a second depth less than the first depth over the field region;

a source electrode coupled to the fin portion of the semiconductor pillar in the device region and disposed over the field insulator in the field region, wherein the source electrode has a third depth over the device region and a fourth depth less than the third depth over the field region; and

a drain electrode coupled to the fin portion of the semiconductor pillar in the device region and disposed over the field insulator in the field region, wherein the drain electrode has a fifth depth over the device region and a sixth depth less than the fifth depth over the field region,

wherein the fin portion of the semiconductor pillar comprises a channel region adjacent to the gate electrode, and a source region and a drain region on opposite sides of the channel region, wherein the source region is adjacent to the source electrode, and wherein the drain region is adjacent to the drain electrode.

6. The microprocessor of claim 5 , wherein the field insulator has a top surface at a first height above a surface of the substrate, wherein the fin portion of the semiconductor pillar has a bottom surface at a second height above the surface of the substrate and a top surface at a third height above the surface of the substrate, and the first height is between the second height and the third height.

7. The microprocessor of claim 5 , further comprising:

a first conformal insulator layer between the base portion of the semiconductor pillar and the field insulator, wherein the first conformal insulator layer is in contact with the base portion of the semiconductor pillar;

a second conformal insulator layer between the base portion of the semiconductor pillar and the field insulator, wherein the second conformal insulator layer is in contact with the first conformal insulator layer and the field insulator; and

a gate dielectric disposed between the gate electrode and the fin portion of the semiconductor pillar, wherein the gate electrode comprises a bulk material and a work function material disposed between the bulk material and the gate dielectric.

8. A mobile computing platform comprising:

a microprocessor comprising:

a semiconductor pillar disposed over a device region of a substrate, the semiconductor pillar having a base portion and a fin portion,

a field insulator disposed over a field region of the substrate and adjacent to the base portion of the semiconductor pillar;

a gate electrode coupled to the fin portion of the semiconductor pillar in the device region and disposed over the field insulator in the field region, wherein the gate electrode has a first depth over the device region and a second depth less than the first depth over the field region;

a source electrode coupled to the fin portion of the semiconductor pillar in the device region and disposed over the field insulator in the field region, wherein the source electrode has a third depth over the device region and a fourth depth less than the third depth over the field region;

a drain electrode coupled to the fin portion of the semiconductor pillar in the device region and disposed over the field insulator in the field region, wherein the drain electrode has a fifth depth over the device region and a sixth depth less than the fifth depth over the field region,

wherein the fin portion of the semiconductor pillar comprises a channel region adjacent to the gate electrode, and a source region and a drain region on opposite sides of the channel region, wherein the source region is adjacent to the source electrode, and wherein the drain region is adjacent to the drain electrode;

a display screen communicatively coupled to the microprocessor; and

a wireless transceiver communicatively coupled to the microprocessor.

9. The mobile computing platform of claim 8 , wherein the field insulator has a top surface at a first height above a surface of the substrate, wherein the fin portion of the semiconductor pillar has a bottom surface at a second height above the surface of the substrate and a top surface at a third height above the surface of the substrate, and the first height is between the second height and the third height.

10. The mobile computing platform of claim 8 , further comprising:

a first conformal insulator layer between the base portion of the semiconductor pillar and the field insulator, wherein the first conformal insulator layer is in contact with the base portion of the semiconductor pillar;

a second conformal insulator layer between the base portion of the semiconductor pillar and the field insulator, wherein the second conformal insulator layer is in contact with the first conformal insulator layer and the field insulator; and

a gate dielectric disposed between the gate electrode and the fin portion of the semiconductor pillar, wherein the gate electrode comprises a bulk material and a work function material disposed between the bulk material and the gate dielectric.

11. A method of fabricating an integrated circuit, the method comprising:

forming a conformal insulator layer adjacent to a semiconductor pillar disposed on a substrate;

forming a field insulator adjacent to the conformal insulator layer;

performing a first selective etch to remove at least a portion of the conformal insulator layer to expose a fin portion of the semiconductor pillar;

performing a second selective etch to remove at least a portion of the field insulator adjacent to the fin portion of the semiconductor pillar; and

forming a gate electrode coupled to the fin portion of the semiconductor pillar and disposed over the field insulator, wherein the gate electrode has a first depth over the conformal insulator layer and a second depth less than the first depth over the field insulator.

12. The method of claim 11 , wherein the field insulator has a top surface at a first height above a surface of the substrate, wherein the fin portion of the semiconductor pillar has a top surface at a second height above the surface of the substrate, and wherein the first height is substantially equal to the second height.

13. The method of claim 11 , wherein the field insulator has a top surface at a first height above a surface of the substrate, wherein the fin portion of the semiconductor pillar has a bottom surface at a second height above the surface of the substrate and a top surface at a third height above the surface of the substrate, and wherein the first height is greater than a height 30% from the second height to the third height.

14. The method of claim 11 , further comprising:

forming, prior to forming the conformal insulator layer, a second conformal insulator layer over the semiconductor pillar, wherein performing the second selective etch removes at least a portion of the second conformal insulator layer adjacent to the fin portion of the semiconductor pillar.

15. The method of claim 11 , further comprising:

forming, prior to forming the conformal insulator layer, a second conformal insulator layer over the semiconductor pillar, wherein the second conformal insulator layer comprises an oxide, wherein forming the conformal insulator layer comprises forming the conformal insulator layer over the second conformal insulator layer, wherein the conformal insulator layer comprises a nitride, and wherein performing the second selective etch removes at least a portion of the second conformal insulator layer adjacent to the fin portion of the semiconductor pillar.

16. The method of claim 11 , further comprising:

forming the semiconductor pillar by patterning a hardmask over a bulk substrate and etching a portion of the bulk substrate to form the semiconductor pillar, wherein a portion of the hardmask is disposed on the semiconductor pillar, and wherein performing the first selective etch removes the portion of hardmask over the semiconductor pillar.

17. The method of claim 11 , further comprising:

forming the semiconductor pillar by patterning a hardmask over a bulk substrate and etching a portion of the bulk substrate to form the semiconductor pillar, wherein a portion of the hardmask is disposed on the semiconductor pillar; and

forming, prior to forming the conformal insulator layer, a second conformal insulator layer over the semiconductor pillar, wherein forming the conformal insulator layer comprises forming the conformal insulator layer over the second conformal insulator layer,

wherein forming the field insulator adjacent to the conformal insulator comprises depositing a bulk field insulator and polishing the bulk field insulator to form the field insulator and to expose the portion of the hardmask, a portion of the conformal insulator layer, and a portion of the second conformal insulator layer,

wherein performing the first selective etch removes the portion of hardmask over the semiconductor pillar, and

wherein performing the second selective etch removes at least a portion of the second conformal insulator layer adjacent to the fin portion of the semiconductor pillar.

18. The method of claim 11 , further comprising:

forming the semiconductor pillar by patterning a hardmask over a bulk substrate and etching a portion of the bulk substrate to form the semiconductor pillar, wherein a portion of the hardmask is disposed on the semiconductor pillar; and

forming, prior to forming the conformal insulator layer, a second conformal insulator layer over the semiconductor pillar, wherein the second conformal insulator layer comprises an oxide, wherein forming the conformal insulator layer comprises forming the conformal insulator layer over the second conformal insulator layer, and wherein the conformal insulator layer comprises a nitride;

wherein forming the field insulator adjacent to the conformal insulator comprises depositing a bulk field insulator and polishing the bulk field insulator to form the field insulator and to expose the portion of the hardmask, a portion of the conformal insulator layer, and a portion of the second conformal insulator layer, and wherein the field insulator comprises an oxide,

wherein performing the first selective etch removes the portion of hardmask over the semiconductor pillar,

wherein performing the second selective etch removes at least a portion of the second conformal insulator layer adjacent to the fin portion of the semiconductor pillar, and

wherein the field insulator has a top surface at a first height above a surface of the substrate, wherein the fin portion of the semiconductor pillar has a bottom surface at a second height above the surface of the substrate and a top surface at a third height above the surface of the substrate, and wherein the first height is at least one of substantially equal to the third height, greater than a midpoint between the second height and the third height, or greater than a height 30% from the second height to the third height.