STORING DATA FROM CACHE LINES TO MAIN MEMORY BASED ON MEMORY ADDRESSES
A method for performing memory operations is provided. One or more processors can determine that at least a portion of data stored in a cache memory of the one or more processors is to be stored in the main memory. One or more ranges of addresses of the main memory is determined that correspond to a plurality of cache lines in the cache memory. A set of cache lines corresponding to addresses in the one or more ranges of addresses is identified, so that data stored in the identified set can be stored in the main memory. For each cache line of the identified set having data that has been modified since that cache line was first loaded to the cache memory or since a previous store operation, data stored in that cache line is caused to be stored in the main memory.
1 . A method of performing memory operations, the method being performed by one or more processors and comprising:
determining that at least a portion of data stored in a cache memory of the one or more processors is to be stored in a main memory;
determining one or more ranges of addresses of the main memory, the addresses of the main memory corresponding to a plurality of cache lines in the cache memory;
identifying a set of cache lines corresponding to addresses in the one or more ranges of addresses, so that data stored in the identified set of cache lines of the cache memory can be stored in the main memory; and
for each cache line of the identified set having data that has been modified since that cache line was first loaded to the cache memory or since a previous store operation, causing data stored in that cache line to be stored in the main memory.
2 . The method of claim 1 , wherein the main memory corresponds to a nonvolatile memory.
3 . The method of claim 1 , wherein the main memory corresponds to a non-volatile memory having a first address range and a volatile memory having a second address range, and wherein the determined one or more ranges of addresses is within the first address range.
4 . The method of claim 1 , wherein determining one or more ranges of addresses corresponding to a main memory includes determining a beginning address and an end address for each of the one or more ranges of addresses.
5 . The method of claim 1 , wherein determining one or more ranges of addresses corresponding to a main memory includes (i) determining a particular address and a mask, and (ii) determining which addresses match the particular address in bit positions specified by the mask.
6 . The method of claim 5 , wherein the mask is determined from a fixed predetermined set of masks.
7 . A method of performing memory operations, the method being performed by one or more processors and comprising:
determining that at least a portion of data stored in a cache memory of the one or more processors is to be stored in a main memory;
determining one or more ranges of addresses of the main memory, the addresses of the main memory corresponding to a plurality of cache lines in the cache memory;
providing the determined one or more addresses or one or more ranges of addresses to the cache memory to enable the cache memory to identify a set of cache lines corresponding to addresses, so that data stored in the identified set of cache lines of the cache memory can be stored in the main memory; and
for each cache line of the identified set having data that has been modified since that cache line was first loaded to the cache memory or since a previous store operation, causing data stored in that cache line to be stored in the main memory.
8 . The method of claim 7 , wherein the main memory corresponds to a non-volatile memory.
9 . The method of claim 7 , wherein the main memory corresponds to a non-volatile memory having a first address range and a volatile memory having a second address range, and wherein the determined one or more ranges of addresses is within the first address range.
10 . The method of claim 7 , wherein determining one or more ranges of addresses corresponding to a main memory includes determining a beginning address and an end address for each of the one or more ranges of addresses.
11 . The method of claim 7 , wherein determining one or more ranges of addresses corresponding to a main memory includes (i) determining a particular address and a mask, and (ii) determining which addresses match the particular address in bit positions specified by the mask.
12 . The method of claim 11 , wherein the mask is specified to be a set of high order bits.
13 . A system comprising:
a main memory;
a processor coupled to the main memory, the processor including a cache memory, the processor to:
determine that at least a portion of data stored in the cache memory of the one or more processors is to be stored in the main memory;
determine one or more ranges of addresses of the main memory, the addresses of the main memory corresponding to a plurality of cache lines in the cache memory;
identify a set of cache lines corresponding to addresses in the one or more ranges of addresses, so that data stored in the identified set of cache lines of the cache memory can be stored in the main memory; and
for each cache line of the identified set having data that has been modified since that cache line was first loaded to the cache memory or since a previous store operation, cause data stored in that cache line to be stored in the main memory.
14 . The system of claim 13 , wherein the main memory corresponds to a non-volatile memory having a first address range and a volatile memory having a second address range, and wherein the determined one or more ranges of addresses is within the first address range.
15 . The system of claim 13 , wherein the processor determines one or more ranges of addresses corresponding to a main memory by (i) determining a particular address and a mask, and (ii) determining which addresses match the particular address in bit positions specified by the mask.