Data processing device and data processing method
A code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15 is interchanged with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK. When 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i+1)-th bit from a most significant bit of the 3 bits of code bits is set to a bit b#i, a (#i+1)-th bit from a most significant bit of 3 bits of symbol bits of the one symbol is set to a bit y#i, and a bit b 0 is interchanged with a bit y 1 , a bit b 1 is interchanged with a bit y 0 , and a bit b 2 is interchanged with a bit y 2.
1. A data processing device comprising:
an encoding circuit configured to perform LDPC encoding based on a parity check matrix of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15;
a bit interleaver circuit configured to interchange code bits of the LDPC code in which the code length is 16200 bits and the encoding rate is 8/15 with symbol bits of a symbol corresponding to any of 8 signal points defined by 8-level phase-shift keying (8PSK), and output the interchanged code bits for transmission to a receiving device; and
a transmitting circuit configured to transmit the output interchanged code bits to the receiving device,
wherein, when 3 bits of the code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i+1)-th bit from a most significant bit of the 3 bits of the code bits is set to a bit b#i, a (#i+1)-th bit from a most significant bit of 3 bits of the symbol bits of the one symbol is set to a bit y#i, and the bit interleaver circuit interchanges
a bit b 0 with a bit y 1 ,
a bit b 1 with a bit y 0 , and
a bit b 2 with a bit y 2 ,
wherein the LDPC code includes information bits and parity bits,
wherein the parity check matrix includes an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits,
wherein the information matrix part is shown by a parity check matrix initial value table, and
wherein the parity check matrix initial value table is a table showing positions of elements of 1 of the information matrix part for every 360 columns and is expressed as follows
32 384 430 591 1296 1976 1999 2137 2175 3638 4214 4304 4486 4662 4999 5174 5700 6969 7115 7138 7189
1788 1881 1910 2724 4504 4928 4973 5616 5686 5718 5846 6523 6893 6994 7074 7100 7277 7399 7476 7480 7537
2791 2824 2927 4196 4298 4800 4948 5361 5401 5688 5818 5862 5969 6029 6244 6645 6962 7203 7302 7454 7534
574 1461 1826 2056 2069 2387 2794 3349 3366 4951 5826 5834 5903 6640 6762 6786 6859 7043 7418 7431 7554
14 178 675 823 890 930 1209 1311 2898 4339 4600 5203 6485 6549 6970 7208 7218 7298 7454 7457 7462
4075 4188 7313 7553
5145 6018 7148 7507
3198 4858 6983 7033
3170 5126 5625 6901
2839 6093 7071 7450
11 3735 5413
2497 5400 7238
2067 5172 5714
1889 7173 7329
1795 2773 3499
2695 2944 6735
3221 4625 5897
1690 6122 6816
5013 6839 7358
1601 6849 7415
2180 7389 7543
2121 6838 7054
1948 3109 5046
272 1015 7464 .
2. The data processing device according to claim 1 ,
wherein the bit interleaver circuit interchanges the code bits of 3×1 bits of the LDPC code that is written in a column direction and read in a row direction of a storage unit including three columns that store 3×1 bits in the row direction and that store 16200/(3×1) bits in the column direction.
3. A data processing device comprising:
an encoding circuit configured to perform LDPC encoding based on a parity check matrix of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15;
a bit interleaver circuit configured to interchange code bits of the LDPC code in which the code length is 16200 bits and the encoding rate is 8/15 with symbol bits of a symbol corresponding to any of 8 signal points defined by 8-level phase-shift keying (8PSK), and output the interchanged code bits for transmission to a receiving device; and
a transmitting circuit configured to transmit the output interchanged code bits to the receiving device,
wherein, when 3 bits of the code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i+1)-th bit from a most significant bit of the 3 bits of the code bits is set to a bit b#i, a (#i+1)-th bit from a most significant bit of 3 bits of symbol bits of the one symbol is set to a bit y#i, and the bit interleaver circuit interchanges
a bit b 0 with a bit y 1 ,
a bit b 1 with a bit y 0 , and
a bit b 2 with a bit y 2 ,
wherein the LDPC code includes information bits and parity bits,
wherein the parity check matrix includes an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits,
wherein the information matrix part is shown by a parity check matrix initial value table, and
wherein the parity check matrix initial value table is a table showing positions of elements of 1 of the information matrix part for every 360 columns and is expressed as follows
32 384 430 591 1296 1976 1999 2137 2175 3638 4214 4304 4486 4662 4999 5174 5700 6969 7115 7138 7189
1788 1881 1910 2724 4504 4928 4973 5616 5686 5718 5846 6523 6893 6994 7074 7100 7277 7399 7476 7480 7537
2791 2824 2927 4196 4298 4800 4948 5361 5401 5688 5818 5862 5969 6029 6244 6645 6962 7203 7302 7454 7534
574 1461 1826 2056 2069 2387 2794 3349 3366 4951 5826 5834 5903 6640 6762 6786 6859 7043 7418 7431 7554
14 178 675 823 890 930 1209 1311 2898 4339 4600 5203 6485 6549 6970 7208 7218 7298 7454 7457 7462
4075 4188 7313 7553
5145 6018 7148 7507
3198 4858 6983 7033
3170 5126 5625 6901
2839 6093 7071 7450
11 3735 5413
2497 5400 7238
2067 5172 5714
1889 7173 7329
1795 2773 3499
2695 2944 6735
3221 4625 5897
1690 6122 6816
5013 6839 7358
1601 6849 7415
2180 7389 7543
2121 6838 7054
1948 3109 5046
272 1015 7464 .
4. A data processing device comprising:
an encoding circuit configured to perform LDPC encoding based on a parity check matrix of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15;
a bit interleaver circuit configured to interchange code bits of the LDPC code in which the code length is 16200 bits and the encoding rate is 8/15with symbol bits of a symbol corresponding to any of 16 signal points defined by 16-ary Amplitude and Phase Shift Keying (16APSK), and output the interchanged code bits for transmission to a receiving device; and
a transmitting circuit configured to transmit the output interchanged code bits to the receiving device
wherein, when 4 bits of the code bits stored in four units of storages having a storage capacity of 16200/4 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i+1)-th bit from a most significant bit of the 4 bits of the code bits is set to a bit b#i, a (#i+1)-th bit from a most significant bit of 4 bits of the symbol bits of the one symbol is set to a bit y#i, and the bit interleaver circuit interchanges
a bit b 0 with a bit y 2 ,
a bit b 1 with a bit y 1 ,
a bit b 2 with a bit y 0 , and
a bit b 3 with a bit y 3 ,
wherein the LDPC code includes information bits and parity bits,
wherein the parity check matrix includes an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits,
wherein the information matrix part is shown by a parity check matrix initial value table, and
wherein the parity check matrix initial value table is a table showing positions of elements of 1 of the information matrix part for every 360 columns and is expressed as follows
32 384 430 591 1296 1976 1999 2137 2175 3638 4214 4304 4486 4662 4999 5174 5700 6969 7115 7138 7189
1788 1881 1910 2724 4504 4928 4973 5616 5686 5718 5846 6523 6893 6994 7074 7100 7277 7399 7476 7480 7537
2791 2824 2927 4196 4298 4800 4948 5361 5401 5688 5818 5862 5969 6029 6244 6645 6962 7203 7302 7454 7534
574 1461 1826 2056 2069 2387 2794 3349 3366 4951 5826 5834 5903 6640 6762 6786 6859 7043 7418 7431 7554
14 178 675 823 890 930 1209 1311 2898 4339 4600 5203 6485 6549 6970 7208 7218 7298 7454 7457 7462
4075 4188 7313 7553
5145 6018 7148 7507
3198 4858 6983 7033
3170 5126 5625 6901
2839 6093 7071 7450
11 3735 5413
2497 5400 7238
2067 5172 5714
1889 7173 7329
1795 2773 3499
2695 2944 6735
3221 4625 5897
1690 6122 6816
5013 6839 7358
1601 6849 7415
2180 7389 7543
2121 6838 7054
1948 3109 5046
272 1015 7464 .
5. The data processing device according to claim 4 ,
wherein the bit interleaver circuit interchanges the code bits of 4×1 bits of the LDPC code that is written in a column direction and read in a row direction of a storage unit including four columns that store 4×1 bits in the row direction and that store 16200/(4×1) bits in the column direction.
6. A data processing method comprising:
performing, by an encoding circuit, LDPC encoding based on a parity check matrix of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15;
interchanging, by a bit interleaver circuit, code bits of the LDPC code in which the code length is 16200 bits and the encoding rate is 8/15 with symbol bits of a symbol corresponding to any of 16 signal points defined by 16-ary Amplitude and Phase Shift Keying (16APSK);
outputting the interchanged code bits for transmission to a receiving device; and
transmitting, by a transmitting circuit, the output interchanged code bits to the receiving device,
wherein, in the interchanging, when 4 bits of the code bits stored in four units of storages having a storage capacity of 16200/4 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i+1)-th bit from a most significant bit of the 4 bits of the code bits is set to a bit b#i, a (#i+1)-th bit from a most significant bit of 4 bits of the symbol bits of the one symbol is set to a bit y#i,
a bit b 0 is interchanged with a bit y 2 ,
a bit b 1 is interchanged with a bit y 1 ,
a bit b 2 is interchanged with a bit y 0 , and
a bit b 3 is interchanged with a bit y 3 ,
wherein the LDPC code includes information bits and parity bits,
wherein the parity check matrix includes an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits,
wherein the information matrix part is shown by a parity check matrix initial value table, and
wherein the parity check matrix initial value table is a table showing positions of elements of 1 of the information matrix part for every 360 columns and is expressed as follows
32 384 430 591 1296 1976 1999 2137 2175 3638 4214 4304 4486 4662 4999 5174 5700 6969 7115 7138 7189
1788 1881 1910 2724 4504 4928 4973 5616 5686 5718 5846 6523 6893 6994 7074 7100 7277 7399 7476 7480 7537
2791 2824 2927 4196 4298 4800 4948 5361 5401 5688 5818 5862 5969 6029 6244 6645 6962 7203 7302 7454 7534
574 1461 1826 2056 2069 2387 2794 3349 3366 4951 5826 5834 5903 6640 6762 6786 6859 7043 7418 7431 7554
14 178 675 823 890 930 1209 1311 2898 4339 4600 5203 6485 6549 6970 7208 7218 7298 7454 7457 7462
4075 4188 7313 7553
5145 6018 7148 7507
3198 4858 6983 7033
3170 5126 5625 6901
2839 6093 7071 7450
11 3735 5413
2497 5400 7238
2067 5172 5714
1889 7173 7329
1795 2773 3499
2695 2944 6735
3221 4625 5897
1690 6122 6816
5013 6839 7358
1601 6849 7415
2180 7389 7543
2121 6838 7054
1948 3109 5046
272 1015 7464 .