Current-mode bandgap reference with proportional to absolute temperature current and zero temperature coefficient current generation

1. A current-mode bandgap reference integrated circuit comprising:

a bandgap voltage generator configured to generate a bandgap voltage;

a zero-temperature coefficient current generator configured to generate a zero-temperature coefficient current;

a proportional to absolute temperature current generator configured to generate a proportional to absolute temperature current;

a first pair of biopolar junction transistors (BJT) comprising a first BJT and a second BJT;

a second pair of bipolar junction transistors, comprising a third BJT and a fourth BJT, wherein said first pair of BJTs matches said second pair of BJTs; and

a first error amplifier, wherein a first input of said first error amplifier is coupled with a collector of at least one BJT of said first BJT pair, wherein a second input of said first error amplifier is coupled through a first resistor to a collector of at least one BJT of said second BJT pair, and wherein an output of said first error amplifier is coupled to a gate of a first p-channel metal oxide semiconductor (PMOS) device and a gate of a second PMOS device.

2. The current-mode bandgap reference integrated circuit of claim 1 , wherein a ratio of said first BJT pair matches a ratio of said second BJT pair.

3. The current-mode bandgap reference integrated circuit of claim 1 , wherein a first side of said first resistor is coupled to a drain of said second PMOS device, and wherein a second side of said first resistor is coupled to the collector of said at least one BJT of said second BJT pair.

4. The current-mode bandgap reference integrated circuit of claim 3 , further comprising: a plurality of components configured to provide Beta cancellation for said proportional to absolute temperature current.

5. The current-mode bandgap reference integrated circuit of claim 1 , further comprising: a second error amplifier, wherein a first input of said second error amplifier is coupled to a collector of said first BJT, and wherein a second input of said second error amplifier is coupled to a collector of said second BJT.

6. The current-mode bandgap reference integrated circuit of claim 5 , wherein said second error amplifier is configured to drive an n-channel metal oxide semiconductor (NMOS) device, and wherein a source of said NMOS device is coupled to said collector of said second BJT.

7. The current-mode bandgap reference integrated circuit of claim 5 , wherein said second error amplifier is configured to drive a third PMOS device, and wherein a drain of said third PMOS device is coupled to said collector of said second BJT.

8. The current-mode bandgap reference integrated circuit of claim 5 , further comprising:

a fifth BJT and a sixth BJT, wherein bases of said fifth BJT and said sixth BJT are each coupled to said collector of said second BJT.

9. The current-mode bandgap reference integrated circuit of claim 8 , further comprising: four identical n-channel metal oxide semiconductor (NMOS) devices configured as source followers which provide matching voltages at their respective sources, wherein a source of a first of said four NMOS devices is coupled to said collector of said second BJT, a source of a second of said four NMOS devices is coupled to a collector of said fourth BJT, a source of a third of said four NMOS devices is coupled to a collector of said fifth BJT, and a source of a fourth of said four NMOS devices is coupled to a collector of said sixth BJT.

10. An input device, said input device comprising:

a plurality of sensor electrodes disposed in a sensor electrode pattern; and

a processing system coupled with said plurality of sensor electrodes, said processing system configured to:

sense capacitive inputs from said sensor electrodes; and

determine a position of an input object relative to said sensor electrode pattern based on said sensed capacitive inputs; and

a current-mode bandgap reference integrated circuit coupled with said processing system, said integrated circuit comprising:

a bandgap voltage generator configured to generate a bandgap voltage;

a zero-temperature coefficient current generator configured to generate a zero-temperature coefficient current;

a proportional to absolute temperature current generator configured to generate a proportional to absolute temperature current;

a first pair of bipolar junction transistors (BJT) comprising a first BJT and a second BJT;

a second pair of bipolar junction transistors, comprising a third BJT and a fourth BJT, wherein said first pair of BJTs matches said second pair of BJTs,

wherein said integrated circuit provides one or more of said bandgap voltage, said zero-temperature current, and said proportional to absolute temperature current for use by said processing system; and

a first error amplifier, wherein a first input of said first error amplifier is coupled with a collector of at least one BJT of said first BJT pair, wherein a second input of said first error amplifier is coupled through a first resistor to a collector of at least one BJT of said second BJT pair, and wherein an output of said first error amplifier is coupled to a gate of a first p-channel metal oxide semiconductor (PMOS) device and a gate of a second PMOS device.

11. The input device of claim 10 , wherein a ratio of said first BJT pair matches a ratio of said second BJT pair.

12. The input device of claim 10 , wherein a first side of said first resistor is coupled to a drain of said second PMOS device, and wherein a second side of said first resistor is coupled to the collector of said at least one BJT of said second BJT pair.

13. The input device of claim 12 , wherein within said integrated circuit: a first plurality of components are configured to provide Beta cancellation for said first resistor; and a second plurality of components are configured to provide Beta cancellation for said proportional to absolute temperature current.

14. The input device of claim 10 , said integrated circuit further comprises: a second error amplifier, wherein a first input of said second error amplifier is coupled to a collector of said first BJT, and wherein a second input of said second error amplifier is coupled to a collector of said second BJT.

15. The current-mode bandgap reference integrated circuit of claim 14 , wherein said second error amplifier is configured to drive an n-channel metal oxide semiconductor (NMOS) device, and wherein a source of said NMOS device is coupled to said collector of said second BJT.

16. The input device of claim 14 , wherein said second error amplifier is configured to drive a third PMOS device, and wherein a drain of said third PMOS device is coupled to said collector of said second BJT.

17. The input device of claim 14 , wherein said integrated circuit further comprises: a fifth BJT and a sixth BJT, wherein bases of said fifth BJT and said sixth BJT are each coupled to said collector of said second BJT.

18. The input device of claim 17 , wherein said integrated circuit further comprises: four identical n-channel metal oxide semiconductor (NMOS) devices configured as source followers which provide matching voltages at their respective sources, wherein a source of a first of said four NMOS devices is coupled to said collector of said second BJT, a source of a second of said four NMOS devices is coupled to a collector of said fourth BJT, a source of a third of said four NMOS devices is coupled to a collector of said fifth BJT, and a source of a fourth of said four NMOS devices is coupled to a collector of said sixth BJT.