50 Gb/s Ethernet using serializer/deserializer lanes
View Patent ↗Systems, devices, and methods of implementing 50 Gb/s Ethernet using serializer/deserializer lanes are disclosed. One such device includes circuitry operable to provide a media access control (MAC) interface. The MAC interface is associated with a port having a 50 Gb/s link rate. The device also includes circuitry operable to generate Ethernet frames from data received at the MAC interface and circuitry operable to distribute the Ethernet frames across a group of serial/deserializer (SERDES) lanes associated with the port, the group having size N. The device also includes circuitry operable to transmit the distributed Ethernet frames on each of the SERDES lanes at a 50/N Gb/s rate.
1. A device comprising:
circuitry configured to
receive Ethernet frames on each of a plurality of serializer/deserializer (SERDES) lanes at a M/N Gb/s rate, where M is a value greater than or equal to 10 and N is a number of the SERDES lanes;
bond the SERDES lanes into a stream of received Ethernet frames; and
provide data from the bonded stream of Ethernet frames to a MAC port having an M Gb/s rate.
2. The device of claim 1 , wherein
each of the plurality of SERDES lanes are associated with a single port.
3. The device of claim 1 , wherein
the circuitry is configured to demultiplex the Ethernet frames received on each of the plurality of SERDES lanes.
4. The device of claim 1 , wherein
the circuitry is configured to demultiplex the Ethernet frames received on each of the plurality of SERDES lanes to a plurality of Physical Coding Sublayer (PCS) lanes.
5. The device of claim 4 , wherein
the circuitry is configured to align the plurality of PCS lanes.
6. The device of claim 4 , wherein
the circuitry is configured to align the plurality of PCS lanes using alignment markers included in blocks that encode the Ethernet frames.
7. The device of claim 6 , wherein
the circuitry is configured to remove the alignment markers after aligning the plurality of PCS lanes.
8. The device of claim 7 , wherein
the circuitry is configured to bond the aligned plurality of PCS lanes after the alignment markers have been removed to form the stream of received Ethernet frames.
9. The device of claim 1 ,
M is 50.
10. The device of claim 1 , wherein
N is 2 or 4.
11. The device of claim 1 , wherein
the plurality of SERDES lanes are arranged to electrically couple to a corresponding plurality of SERDES lanes on a midplane of a blade server chassis.
12. The device of claim 11 , wherein
each of the SERDES lanes on the midplane is associated with an electrical trace group on the midplane.
13. The device of claim 12 , wherein
each of electrical trace group includes a transmit differential pair and a receive differential pair.
14. The device of claim 1 , wherein
the received Ethernet frames are distributed across the plurality of SERDES lanes using Multi-Lane Distribution across a plurality of Physical Coding Sublayer (PCS) lanes.
15. The device of claim 1 , wherein
the device is configured to support another link rate lower than M Gb/s and to autonegotiate between the link rates.
16. The device of claim 15 , wherein
the autonegotiation is conducted on a lane 0 of the SERDES lanes.
17. The device of claim 15 , wherein
the autonegotiation is conducted in accordance with IEEE 802.3an.
18. A method comprising:
receiving Ethernet frames on each of a plurality of serializer/deserializer (SERDES) lanes at a M/N Gb/s rate, where M is a value greater than or equal to 10 and N is a number of the SERDES lanes;
bonding the SERDES lanes into a stream of received Ethernet frames; and
providing data from the bonded stream of Ethernet frames to a MAC port having an M Gb/s rate.
19. The method of claim 18 , further comprising:
demultiplexing the Ethernet frames received on each of the plurality of SERDES lanes to a plurality of Physical Coding Sublayer (PCS) lanes;
align the plurality of PCS lanes using alignment markers included in blocks that encode the Ethernet frames; and
remove the alignment markers after aligning the plurality of PCS lanes.
20. A device comprising
circuitry configured to
generate Ethernet frames from data received at a media access control (MAC) interface associated with a port having an M Gb/s link rate, M being a value greater than or equal to 10;
distribute the Ethernet frames across a group of serializer/deserializer (SERDES) lanes associated with the port, the group having a size N which is greater than 1;
transmit the distributed Ethernet frames on each of the SERDES lanes at an M/N Gb/s rate;
receive Ethernet frames on each of the SERDES lanes at a M/N Gb/s rate;
bond the SERDES lanes into a stream of received Ethernet frames; and
provide data from the bonded stream of Ethernet frames to the MAC port at an M Gb/s rate.