Above motherboard interposer with quarter wavelength electrical paths
A multi-layer interposer substrate includes multiple layers of single interposer substrates. Each single interposer substrate has a first array of interposer interconnects, each interposer interconnect in the first array of interposer interconnects corresponding to interconnects in an array of processor interconnects, a second array of interposer interconnects, each interposer interconnect in the second array of the interposer interconnects corresponding to an array of circuit interconnects on a circuit substrate, and at least one conductive trace in the interposer substrate in connection with at least one interconnect in the first array of interposer interconnects. The conductive trace has a parallel portion parallel to the interposer substrate such that no electrical connection exists between the interconnect and a corresponding one of the interposer interconnects in the second array of interposer interconnects. An array of connections for a peripheral circuit on each single interposer is connected to the at least one conductive trace.
1. A multi-layer interposer substrate, comprising:
multiple layers of single interposer substrates stacked to form the multi-layer interposer substrate, each single interposer substrate, comprising:
a first array of interposer interconnects in the single interposer substrate, each interposer interconnect in the first array of interposer interconnects corresponding to interconnects in an array of processor interconnects;
a second array of interposer interconnects in the single interposer substrate, each interposer interconnect in the second array of the interposer interconnects corresponding to an array of circuit interconnects on a circuit substrate; and
at least one conductive trace in the interposer substrate in connection with at least one interconnect in the first array of interposer interconnects, the conductive trace arranged to have a parallel portion parallel to the interposer substrate such that no electrical connection exists between the interconnect and a corresponding one of the interposer interconnects in the second array of interposer interconnects; and
an array of connections for a peripheral circuit on each single interposer connected to the at least one conductive trace.
2. The multi-layer interposer substrate of claim 1 , wherein a path distance for each array of connections for the peripheral circuit on each single interposer has a same path length to the array of processor interconnects.
3. The multi-layer interposer substrate of claim 1 , wherein the multiple layers comprise two layers that split on opposite sides of the multi-layer interposer.
4. The multi-layer interposer substrate of claim 1 , wherein the single interposer substrates are folded.
5. The multi-layer interposer substrate of claim 1 , wherein the multi-layer interposer substrate has a first split into subsets of single interposers, and each subset has a second split into single interposers.