Electronic systems with through-substrate interconnects and MEMS device
View Patent ↗Disclosed are systems, methods, and computer program products for electronic systems with through-substrate interconnects and mems device. An interconnect formed in a substrate having a first surface and a second surface, the interconnect includes: a bulk region; a via extending from the first surface to the second surface; an insulating structure extending through the first surface into the substrate and defining a closed loop around the via, wherein the insulating structure comprises a seam portion separated by at least one solid portion; and an insulating region extending from the insulating structure toward the second surface, the insulating region separating the via from the bulk region, wherein the insulating structure and insulating region collectively provide electrical isolation between the via and the bulk region.
1. A through-silicon via (TSV) structure formed in a substrate having a first surface and a second surface, the TSV structure comprising:
a bulk region;
a via extending from the first surface to the second surface;
an insulating structure defining a closed loop extending around the via and through the first surface into the substrate, wherein in a plan view the insulating structure comprises a first seam portion and a first solid portion, the first seam portion and the first solid portion forming at least a portion of the closed loop; and
an insulating region extending from the insulating structure toward the second surface, the insulating region separating the via from the bulk region,
wherein the insulating structure and insulating region collectively provide electrical isolation between the via and the bulk region,
wherein the first seam portion comprises an outer insulator, an inner insulator, and at least one seam having a first end and a second end opposing the first end,
wherein in the plan view
the first solid portion is between the first end and the second end, thereby separating the first end and the second end, and
the at least one seam is positioned between the outer insulator and the inner insulator.
2. The TSV structure of claim 1 , wherein the first seam portion comprises at least one void.
3. The TSV structure of claim 1 , wherein in the plan view the insulating structure further comprises a second seam portion having a third end and a fourth end opposing the third end, and a second solid portion separating the third end and the fourth end of the second seam portion.
4. The TSV structure of claim 1 , wherein in the plan view the insulating structure is a rectangle.
5. The TSV structure of claim 1 , wherein in the plan view the insulating structure is an ellipse.
6. The TSV structure of claim 1 , wherein in the plan view the first and second ends are curved inward toward the via.
7. The TSV structure of claim 1 , wherein the insulating region comprises a gaseous material.
8. The TSV structure of claim 1 , wherein the first solid portion comprises silicon dioxide.
9. The TSV structure of claim 1 , wherein the insulating region comprises an upper portion abutting the insulating structure and a lower portion abutting the second surface and the upper portion.
10. The TSV structure of claim 9 , wherein the lower portion comprises a solid material.
11. The TSV structure of claim 10 , further comprising a pad region, wherein the lower portion overlaps the bulk region, and wherein the pad region overlaps the via and the lower portion.
12. The TSV structure of claim 1 , wherein the via comprises doped silicon.
13. The TSV structure of claim 11 , wherein a first cross-sectional area of the pad region along the second surface is greater than a second cross-sectional area of the via along the second surface.
14. The TSV structure of claim 1 , wherein the via comprises a metal conductor.
15. The TSV structure of claim 1 , wherein the first solid portion contacts the first end and the second end of the at least one seam.
16. The TSV structure of claim 1 , wherein an exterior of the first solid portion is substantially aligned relative to an exterior of the outer insulator along the closed loop.
17. The TSV structure of claim 1 , wherein the first solid portion and the first seam portion comprise the same material.
18. An electronic component comprising:
a substrate having a first surface and a second surface, the substrate comprising:
a through-silicon via (TSV) structure formed in the substrate, the TSV structure comprising:
a bulk region;
a via extending from the first surface to the second surface;
an insulating structure defining a closed loop extending around the via and through the first surface into the substrate, wherein in a plan view the insulating structure comprises a first seam portion and a first solid portion, the first seam portion and the first solid portion forming at least a portion of the closed loop; and
an insulating region extending from the insulating structure toward the second surface, the insulating region separating the via from the bulk region,
wherein the insulating structure and insulating region collectively provide electrical isolation between the via and the bulk region,
wherein the first seam portion comprises an outer insulator, an inner insulator, and at least one seam having a first end and a second end opposing the first end,
wherein in the plan view
the first solid portion is between the first end and the second end, thereby separating the first end and the second end, and
the at least one seam is positioned between the outer insulator and the inner insulator.
19. The electronic component of claim 18 , the substrate further comprising a micro-electro-mechanical device, wherein a first portion of the micro-electro-mechanical device is electrically coupled to the via.
20. The electronic component of claim 19 , wherein the insulating structure of the TSV structure electrically isolates a second portion of the micro-electro-mechanical device from the TSV structure.
21. The electronic component of claim 18 , further comprising a package substrate and a chip, wherein the substrate is on the package substrate and the chip is on the substrate and wherein the TSV structure of the substrate electrically couples the chip to the package substrate.
22. The electronic component of claim 18 , wherein the via comprises a metal conductor.
23. The electronic component of claim 18 , wherein the first solid portion contacts the first end and the second end of the at least one seam.
24. The electronic component of claim 18 , wherein an exterior of the first solid portion is substantially aligned relative to an exterior of the outer insulator along the closed loop.
25. The electronic component of claim 18 , wherein the first solid portion and the first seam portion comprise the same material.