IP Library Granted Patent US 9,620,236
Granted Patent B2
US 9,620,236 · App. 14/790,438 · Granted Apr 11, 2017

Level compensation in multilevel memory

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Quick Facts
Patent No.
US 9,620,236
App. No.
14/790,438
Granted
Apr 11, 2017
Kind
B2
Abstract

Some embodiments include apparatuses and methods having a compensation unit to provide a compensation value based at least in part on a threshold voltage value of a memory cell. At least one of such embodiments includes a controller to select a code during an operation of retrieving information from the memory cell to represent a value of information stored in the memory cell. Such a code can be associated with an address having an address value based at least in part on the compensation value. Additional apparatuses and methods are described.

Claims (34)

1. An apparatus comprising:

an input to receive digital information having a first set of values associated with a first threshold voltage value range of a memory cell and a second set of values associated with a second threshold voltage value range of the memory cell;

a first storage component to store a first group of values based on a third set of values of the digital information, and to store a second group of values based on a fourth set of values of the digital information; and

a second storage component to store a first compensation value based on a difference between a first value in the first set of values and a second value in the third set of values, and to store a second compensation value based on a difference between a third value in the second set of values and a fourth value in the fourth set of values.

2. The apparatus of claim 1 , wherein the first group of values and the third set of values include a same number of values.

3. The apparatus of claim 2 , wherein the second group of values and the fourth set of values include a same number of values.

4. The apparatus of claim 1 , wherein the first group of values are in a consecutive order.

5. The apparatus of claim 2 , wherein the second group of values are in a consecutive order.

6. The apparatus of claim 5 , wherein values from the first group of values to values from the second group of values are in a nonconsecutive order.

7. The apparatus of claim 1 , wherein the third set of values of the digital information is associated with a threshold voltage value range of the memory cell.

8. The apparatus of claim 1 , further comprising a controller to select a code during an operation of retrieving information from the memory cell to represent a value of information stored in the memory cell, the code associated with an address having an address value based at least in part on the first compensation value.

9. The apparatus of claim 1 , further comprising a comparator to compare values of the digital information with the first and second groups of values.

10. The apparatus of claim 1 , wherein the first and second storage components include non-volatile memory.

11. The apparatus of claim 1 , wherein the first compensation value is different from the second compensation value.

12. The apparatus of claim 1 , wherein the first compensation value is equal to the second compensation value.

13. An apparatus comprising:

a memory cell; and

a controller to:

obtain a threshold voltage value of the memory cell during an operation of retrieving information from the memory cell;

provide a compensation value based on a relationship between the threshold voltage value and a threshold voltage value range of the memory cell; and

select a code to represent a value of the information, the code stored at a location associated with an address having and address value based at least in part on the compensation value.

14. The apparatus of claim 13 , wherein the controller is to store the information in the memory cell in a write operation performed before the operation of retrieving information from the memory cell, and the threshold voltage value of the memory cell during the operation of retrieving information from the memory cell is different from a threshold voltage value associated with the information in the write operation.

15. A method comprising:

obtaining a threshold voltage value of a memory cell during an operation of retrieving information from the memory cell;

providing a first compensation value if the threshold voltage value is associated with a first threshold voltage value range of the memory cell;

providing a second compensation value if the threshold voltage value is associated with a second threshold voltage value range of the memory cell; and

selecting a code to represent a value of the information, the code stored at a location associated with an address having and address value based at least in part on one of the first and second compensation values.

16. The method of claim 15 , wherein at least one of the first and second compensation values is a positive value.

17. The method of claim 15 , wherein at least one of the first and second compensation values is a negative value.

18. The method of claim 15 , wherein the first compensation value is zero.

19. The method of claim 15 , further comprising:

storing the information in the memory cell in a write operation performed before the operation of retrieving information from the memory cell, wherein the threshold voltage value of the memory cell during the operation of retrieving information from the memory cell is different from a threshold voltage value associated with the information in the write operation.

20. The method of claim 19 , wherein the threshold voltage value of the memory cell during the operation of retrieving information from the memory cell is greater than the threshold voltage value associated with the information in the write operation.

21. The method of claim 19 , wherein the threshold voltage value of the memory cell during the operation of retrieving information from the memory cell is less than the threshold voltage value associated with the information in the write operation.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →