Graphics display system with unified memory architecture
View Patent ↗A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.
1. A memory system comprising:
a memory that is shared by a plurality of devices;
a first memory controller;
a second memory controller;
a memory request arbiter coupled to the memory, wherein the memory request arbiter is configured to perform real time scheduling of memory requests from different devices having different priorities and provides access to the memory by the plurality of devices, the memory request arbiter comprising a first arbiter coupled to the first memory controller and a second arbiter coupled to the second memory controller; and
a memory select circuit configured to:
receive the memory requests from the plurality of devices; and
for each of the memory requests, select one of the first arbiter or the second arbiter using a characteristic of the memory request and provide the memory request to the selected one of the first arbiter or the second arbiter;
a circuit component associated with one or more of the plurality of devices and coupled between the associated devices and the memory request arbiter, wherein the circuit component is configured to enforce a minimum interval between subsequent accesses by the associated device to the memory, the minimum interval configured to prevent a first device of the plurality of devices from accessing the memory during consecutive memory cycles when a second device of the plurality of devices is also requesting access to the memory.
2. The memory system of claim 1 , wherein one or more of the plurality of devices is sensitive to latency and does not have determinable periodic behavior.
3. The memory system of claim 1 , wherein the one or more devices associated with the circuit component include a central processing unit.
4. The memory system of claim 1 , wherein the one or more devices associated with the circuit component make high priority service requests to access the memory through the circuit component.
5. The memory system of claim 1 , further comprising a round robin server for handling low priority tasks.
6. The memory system of claim 1 , wherein the characteristic of the memory request comprises an address of the memory request.
7. The memory system of claim 1 , wherein the circuit component is a block out timer, the block out timer having a period programmable for system tuning.
8. A method comprising:
receiving a plurality of memory requests from a plurality of devices for access to a memory shared by the plurality of devices, the plurality of memory requests having different priorities;
for each of the memory requests, selecting one of a first arbiter or a second arbiter using a characteristic of the memory request;
for each of the memory requests, providing the memory request to the selected one of the first arbiter or the second arbiter;
performing scheduling of the memory requests using the first arbiter and the second arbiter; and
enforcing a minimum interval between accesses of the memory, the minimum interval configured to prevent a first device of the plurality of devices from accessing the memory during consecutive memory cycles when a second device of the plurality of devices is also requesting access to the memory, wherein a circuit component associated with one or more of the plurality of devices is coupled between the associated devices and the memory request arbiter, wherein the circuit component is configured to enforce the minimum interval between subsequent accesses by the associated device to the memory.
9. The method of claim 8 , wherein performing scheduling of the memory requests comprises providing access to the memory by one or more of the plurality of devices sensitive to latency and not having determinable periodic behavior.
10. The method of claim 8 , wherein the one or more devices associated with the circuit component include a central processing unit.
11. The method of claim 8 , wherein the one or more devices associated with the circuit component make high priority service requests to access the memory through the circuit component.
12. The method of claim 8 , further comprising handling low priority tasks using a round robin server.
13. The method of claim 8 , wherein the characteristic of the memory request comprises an address of the memory request.
14. The memory system of claim 8 , wherein the circuit component is a block out timer, the block out timer having a period programmable for system tuning.
15. A memory system comprising:
circuitry configured to:
receive a plurality of memory requests from a plurality of devices for access to a memory shared by the plurality of devices, the plurality of memory requests having different priorities;
for each of the memory requests, select one of a first arbiter or a second arbiter using a characteristic of the memory request, the first arbiter and the second arbiter implemented within the circuitry;
for each of the memory requests, provide the memory request to the selected one of the first arbiter or the second arbiter;
perform scheduling of the memory requests using the first arbiter and the second arbiter; and
enforce a minimum interval between accesses of the memory, the minimum interval configured to prevent a first device of the plurality of devices from accessing the memory during consecutive memory cycles when a second device of the plurality of devices is also requesting access to the memory, wherein the circuitry comprises a circuit component associated with one or more of the plurality of devices and coupled between the associated devices and the memory request arbiter, wherein the circuit component is configured to enforce the minimum interval between subsequent accesses by the associated device to the memory.
16. The memory system of claim 15 , wherein one or more of the plurality of devices is sensitive to latency and does not have determinable periodic behavior.
17. The memory system of claim 15 , wherein the one or more devices associated with the circuit component include a central processing unit.
18. The memory system of claim 15 , wherein the one or more devices associated with the circuit component make high priority service requests to access the memory through the circuit component.
19. The memory system of claim 15 , wherein the characteristic of the memory request comprises an address of the memory request.
20. The memory system of claim 15 , wherein the circuit component is a block out timer, the block out timer having a period programmable for system tuning.