Apparatus, system and method of back side illumination (BSI) complementary metal-oxide-semiconductor (CMOS) pixel array
View Patent ↗Some demonstrative embodiments include devices and/or methods of Back Side Illumination (BSI) Complementary Metal-Oxide-Semiconductor (CMOS) pixel array. For example, a BSI CMOS pixel array may include a plurality of pixels, a pixel of the plurality of pixels may include one or more Metal-Oxide-Semiconductor (MOS) transistors comprising one or more well regions, a well region of the one or more well regions comprising an N-Well (NW) region or a P-well (PW) region; a photodiode; an epitaxial (epi) layer comprising an absorption area and a collection area, the absorption area to absorb incoming photons and to generate electrons responsive to absorbed photons, and the collection area connecting the absorption area to the photodiode to provide the electrons from the absorption area to the photodiode; and a barrier layer separating the absorption area from the one or more well regions.
1. A back-side illumination (BSI) complementary metal-oxide-semiconductor (CMOS) pixel array comprising:
a plurality of pixels, a pixel of said plurality of pixels comprising:
one or more Metal-Oxide-Semiconductor (MOS) transistors comprising one or more well regions, a well region of said one or more well regions comprising an N-Well (NW) region or a P-well (PW) region;
a photodiode;
an epitaxial (epi) layer comprising an absorption area and a collection area, said absorption area to absorb incoming photons and to generate electrons responsive to absorbed photons, and said collection area connecting said absorption area to said photodiode to provide said electrons from said absorption area to said photodiode; and
a barrier layer separating said absorption area from said one or more well regions.
2. The BSI CMOS pixel array of claim 1 , wherein said photodiode comprises a low fill factor (FF) diode.
3. The BSI CMOS pixel array of claim 1 , wherein said collection area extends from said absorption area to said photodiode through said barrier layer.
4. The BSI CMOS pixel array of claim 1 , wherein said collection area is configured to perform the functionality of an electrostatic lens to collect said electrons from said absorption area.
5. The BSI CMOS pixel array of claim 1 , wherein said barrier layer is configured to prevent diffusion of said electrons from said absorption area to said well regions.
6. The BSI CMOS pixel array of claim 1 , wherein a thickness of said epi layer is at least 4 micron (um).
7. The BSI CMOS pixel array of claim 1 , wherein a thickness of said epi layer is at least 10 micron (um).
8. The BSI CMOS pixel array of claim 1 , wherein a thickness of said epi layer is at least 15 micron (um).
9. The BSI CMOS pixel array of claim 1 , wherein a resistivity of said epi layer is greater than 100 ohm to centimeter (ohm-cm).
10. The BSI CMOS pixel array of claim 1 comprising a micro lens, said absorption area is between said micro lens and said barrier layer.
11. The BSI CMOS pixel array of claim 10 comprising an anti-reflective coating (ARC) layer, said ARC layer is between said micro lens and said absorption area.
12. The BSI CMOS pixel array of claim 1 , wherein said one or more MOS transistors comprise one or more transistors selected from a group consisting of one or more P-type MOS (PMOS) transistors and one or more N-type MOS (NMOS) transistors.
13. The BSI CMOS pixel array of claim 1 , wherein said barrier layer comprises a deep PW implant.
14. The BSI CMOS pixel array of claim 1 , wherein said barrier layer comprises a boron implant.
15. The BSI CMOS pixel array of claim 1 , wherein said photodiode comprises a fully pinned diode.
16. A complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) comprising:
a circuitry; and
a back-side illumination (BSI) pixel array comprising:
a plurality of pixels, a pixel of said plurality of pixels comprising:
one or more Metal-Oxide-Semiconductor (MOS) transistors comprising one or more well regions, a well region of said one or more well regions comprising an N-Well (NW) region or a P-well (PW) region;
a photodiode;
an epitaxial (epi) layer comprising an absorption area and a collection area, said absorption area to absorb incoming photons and to generate electrons responsive to said absorbed photons, and said collection area connecting said absorption area to said photodiode to provide said electrons from said absorption area to said photodiode; and
a barrier layer separating said absorption area from said well regions.
17. The CMOS IC of claim 16 comprising a guard ring separating said circuitry from said BSI pixel array.
18. The CMOS IC of claim 17 , wherein said guard ring is configured to prevent diffusion of photoelectrons from said circuitry to said BSI pixel array.
19. An imaging device comprising:
a memory;
an input;
an output;
a processor; and
a complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) comprising:
a circuitry; and
a back-side illumination (BSI) pixel array comprising:
a plurality of pixels, a pixel of said plurality of pixel sensors comprising:
one or more Metal-Oxide-Semiconductor (MOS) transistors comprising one or more well regions, a well region of said one or more well regions comprising an N-Well (NW) region or a P-well (PW) region;
a photodiode;
an epitaxial (epi) layer comprising an absorption area and a collection area, said absorption area to absorb incoming photons and to generate electrons responsive to said absorbed photons, and said collection area connecting said absorption area to said photodiode to provide said electrons from said absorption area to said photodiode; and
a barrier layer separating said absorption area from said well regions.
20. The imaging device of claim 19 comprising a digital camera or a Smartphone.