Variable resistive memory device including vertical channel PMOS transistor

1. A semiconductor device, comprising:

a pillar extending substantially perpendicular from a semiconductor substrate, the pillar including an inner portion extending along a longitude direction of the pillar and an outer portion surrounding entire surface of the inner portion, wherein the outer portion includes an upper outer region positioned over the inner portion, a sidewall region positioned beside the inner portion, and a lower outer region positioned below the inner portion;

a drain formed in the upper outer region of the outer portion;

a source formed in the lower outer region of the outer portion;

a channel region formed in the inner portion;

a gate surrounding the pillar to form a cylinder shape;

a gate insulating layer formed between the gate and the pillar;

a heating electrode formed over the drain; and

a variable resistance layer formed on the heating electrode,

wherein the inner portion includes a semiconductor layer having a lattice constant that is smaller than a lattice constant of the outer portion so that the inner portion is subjected to a compress stress based on a junction with the outer portion.

2. The semiconductor device of claim 1 , wherein the inner portion of the pillar is formed of a first semiconductor layer, and the outer portion of the pillar is formed of a second semiconductor layer and a third semiconductor layer,

wherein the first semiconductor layer has a first lattice constant, the second semiconductor layer has a second lattice constant being larger than the first lattice constant, and the third semiconductor layer has a third lattice constant being lager than the second lattice constant.

3. The semiconductor device of claim 2 , wherein the upper outer region and the lower outer region of the outer portion are formed of the second semiconductor layer and the sidewall region of the outer region is formed of the third semiconductor layer.

4. The semiconductor device of claim 2 , wherein the channel region is formed in the first semiconductor layer, and the drain is formed in the second semiconductor layer.

5. The semiconductor device of claim 2 , wherein at least one of the semiconductor substrate, the second semiconductor layer, and the third semiconductor layer, constituting the outer portion of the pillar, includes a silicon (Si) material.

6. The semiconductor device of claim 5 , wherein the first semiconductor layer includes one selected from the group consisting of SiC, AIN, GaN, ZnS, ZnO, ZnSe, CdS, BP, InN, and CdSe.

7. The semiconductor device of claim 6 , wherein, when the first semiconductor layer is a SiC layer, the first semiconductor layer is formed of a C-low concentration-SiC layer that contains a content of C below a stoichiometric content of C in SiC, a C-high concentration-SiC layer that contains a content of C above the stoichiometric content of C in SiC, and a C-low concentration-SiC layer that contains a content of C below the stoichiometric content of C in SiC, which are sequentially stacked.

8. The semiconductor device of claim 1 , wherein the channel region is formed of a material having a lattice constant smaller than that of at least one of the regions in which the source and drain are formed.