Chip Scale Package
A novel semiconductor chip scale package encapsulates semiconductor chip on the device side, the non-device side, and the four edges with a mold compound. One process to fabricate such a semiconductor chip scale package involves forming trenches on the surface of a wafer around the chips and filling the trenches and covering the device side of the chips with a first mold compound. The wafer is subsequently thinned from the non-device side until the bottom portion of the trenches and the mold compound in the portion are also removed. The thinning process creates a plane that contains the back side of the chips and the mold compound exposed in the trench. This plane is subsequently covered with a second mold compound.
1 . A semiconductor device package, comprising:
a semiconductor chip having a device side with metallic contact bumps thereon, a non-device side opposite the device side, and four edges;
a first layer of mold compound covering the four edges and the device side of the chip;
a second layer of mold compound covering the non-device side of the chip;
the first layer of mold compound joining the second layer of mold compound at a plane that is coplanar to the non-device side of the chip.
2 . The semiconductor device package of claim 1 , in which a top portion of the contact bumps on the device side of the semiconductor chip protrude from the first layer of mold compound.
3 . The semiconductor device package of claim 2 , in which the protruding portion of the contact burns is covered with a metallic film containing gold.
4 . The semiconductor device package of claim 3 , in which the contact bumps contain nickel.
5 . The semiconductor device package of claim 1 , in which the first layer of mold compound contains filler particles.
6 . The semiconductor device package of claim 5 , further comprising partially ground filler particles near the plane where the first layer and the second layer of mold compound meet.
7 . The semiconductor device of claim 6 , in which the partially ground filler particles are embedded in the first layer of mold compound.
8 . The semiconductor device of claim 7 , in which the partially ground filler particles are not embedded in the second mold compound.
9 - 17 . (canceled)
18 . A semiconductor device, comprising:
a semiconductor chip having a device side and four edge and a non-device side;
a first layer of mold compound covering the device side of the chip and extending down the four edges;
a second layer of a different mold compound covering the non-device side of the semiconductor chip and extending from the non-device side, joining the first layer of mold compound.
19 . The semiconductor device of claim 18 , further comprising copper contact on the device side of the semiconductor chip.
20 . The semiconductor device of claim 19 , in which the first layer of mold compound has partially ground filler particles near the second layer of mold compound.
21 . The semiconductor device of claim 20 , in which the partially ground particles form surface co-planar with the non-device side of the semiconductor chip.
22 . A semiconductor device, comprising:
a first mold compound having filler particles; and
partially ground filler particles disposed on a surface of a layer of second mold compound.
23 . The semiconductor device of claim 22 , further comprising a semiconductor chip on the surface of the layer of second mold compound.
24 . The semiconductor device of claim 23 , further comprising metallic contacts on a device side of the semiconductor chip.
25 . The semiconductor device of claim 24 , in which the metallic contacts comprise copper.
26 . The semiconductor device of claim 25 , in which the metallic contacts further comprise gold or platinum.