IP Library Granted Patent US 9,721,975
Granted Patent B2
US 9,721,975 · App. 14/793,477 · Granted Aug 1, 2017

Semiconductor device, display device, and electronic device

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Quick Facts
Patent No.
US 9,721,975
App. No.
14/793,477
Granted
Aug 1, 2017
Kind
B2
Abstract

A semiconductor device including: one or more pieces of first wiring having a main wiring section and a bifurcation wiring section; one or a plurality of pieces of second wiring having a trunk wiring section and a plurality of branch wiring sections within a gap region between the main wiring section and the bifurcation wiring section; one or a plurality of transistors each divided and formed into a plurality of pieces, the plurality of branch wiring sections individually functioning as a gate electrode and the one or plurality of transistors having a source region formed within the main wiring section and within the bifurcation wiring section and having a drain region formed between the plurality of branch wiring sections; and one or a plurality of pieces of third wiring electrically connected to the drain region of the one or plurality of transistors.

Claims (15)

1. A semiconductor device comprising:

a first wiring extending along a first direction on a substrate and having a main wiring section and a bifurcation wiring section arranged so as to be separated from each other;

a second wiring extending along a second direction different from the first direction on the substrate;

a transistor having (a) a source region electrically connected to the main wiring section, (b) a drain region and (c) a gate electrode that extends along the first direction within a gap region between (i) the main wiring section and (ii) the bifurcation wiring section and that is electrically connected to the second wiring, the source region, the drain region and the gate electrode being arranged along the second direction; and

a third wiring extending along the second direction and electrically connected to the drain region of the transistor,

wherein,

the second wiring, the first wiring, and the third wiring are sequentially stacked on the substrate in respective different layers in a third direction orthogonal to the first direction and the second direction.

2. The semiconductor device according to claim 1 , wherein a plurality of the transistors are disposed adjacent for each other along the first direction.

3. The semiconductor device according to claim 1 , wherein the transistor has two gate electrodes.

4. The semiconductor device according to claim 1 , wherein the first wiring has a connecting part for electrically connecting the main wiring section and the bifurcation wiring section to each other within the gap region overlapping the second wiring in a planar view.

5. The semiconductor device according to claim 1 , further comprising a plurality of first wirings, a plurality of transistors, and a buffer circuit as a unit circuit formed of the plurality of the first wirings and the plurality of the transistors.

6. The semiconductor device according to claim 5 , wherein:

each drain region is disposed between the first wirings, and

for each transistor, the gate electrode is disposed between the source region and the drain region and is electrically connected to the second wiring.

7. The semiconductor device according to claim 1 , wherein the gate electrode, the drain region of the transistor, and the third wiring are sequentially stacked on the substrate in respective different layers in the third direction.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2015
From: SOGABE, MITSUFUMI; MURASE, MASAKI; MIZUHASHI, HIROSHI
To: JAPAN DISPLAY INC.
Reel/Frame 036196/0198 →