The described embodiments may provide a chemical detection circuit. The chemical detection circuit may comprise a column of chemically-sensitive pixels. Each chemically-sensitive pixel may comprise a chemically-sensitive transistor, and a row selection device. The chemical detection circuit may further comprise a column interface circuit coupled to the column of chemically-sensitive pixels and an analog-to-digital converter (ADC) coupled to the column interface circuit. Each column interface circuit and column-level ADC may be arrayed with other identical circuits and share critical resources such as biasing and voltage references, thereby saving area and power.
1. A method to reduce error in generating an output signal for a chemical detection integrated circuit chip, comprising:
generating a row selection signal by a row decoder of the chemical detection integrated circuit chip, the chemical detection integrated circuit chip having a pixel array that includes a plurality of rows and columns of chemical detection pixels, each chemical detection pixel including:
a chemically-sensitive transistor; and
a row selection device;
applying the row selection signal to a respective row selection device of a selected chemical detection pixel;
converting an analog signal at a readout signal line of a column of chemical detection pixels to a digital signal by an Analog-to-Digital converter (ADC) on the chemical detection integrated circuit chip-to provide digitized data;
serializing the digitized data in parallel for each column of chemical detection pixels on the chemical detection integrated circuit chip; and
outputting the digitized data as the output signal from the chemical detection integrated circuit chip on a plurality of serial links in parallel.
2. The method of claim 1 , wherein each column of chemical detection pixels has a dedicated ADC.
3. The method of claim 1 , wherein two columns of chemical detection pixels share one ADC by multiplexing.
4. The method of claim 1 , wherein the chemical detection integrated circuit chip includes multiple columns of chemical detection pixels and multiple ADCs, the ADCs are configured to perform AD conversion in parallel.
5. The method of claim 4 , wherein the ADCs share bias reference voltages and signal reference voltages for area and power savings.