IP Library Granted Patent US 9,400,759
Granted Patent B2
US 9,400,759 · App. 14/795,543 · Granted Jul 26, 2016

Cache load balancing in storage controllers

Inventors: Parag R. Maharana (Fremont, CA); Kishore K. Sampathkumar (Bangalore, IN)
Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
G06F13/28G06F12/0246G06F12/0802G06F12/0866G06F13/4221G06F2212/1036G06F2212/222G06F2212/262G06F2212/283G06F2212/604
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Quick Facts
Patent No.
US 9,400,759
App. No.
14/795,543
Granted
Jul 26, 2016
Kind
B2
Abstract

Methods and structure are provided for cache load balancing in storage controllers that utilize Solid State Drive (SSD) caches. One embodiment is a storage controller of a storage system. The storage controller includes a host interface operable to receive Input and Output (I/O) operations from a host computer. The storage controller also includes a cache memory that includes an SSD. Further, the storage controller includes a cache manager that is distinct from the cache memory. The cache manager is able to determine physical locations in the multiple SSDs that are unused, to identify an unused location that was written to a longer period of time ago than other unused locations, and to store a received I/O operation in the identified physical location. Further, the cache manager is able to trigger transmission of the stored I/O operations to storage devices of the storage system for processing.

Claims (72)

1. A storage controller of a storage system, the storage controller comprising:

a host interface operable to receive Input/Output (I/O) operations from a host computer;

a cache memory comprising a Solid State Drive (SSD); and

a cache manager that is operable to determine physical locations in the SSD that are unused, to identify an unused location that was written to a longer period of time ago than other unused locations, and to store a received I/O operation in the identified physical location,

the cache manager further operable to trigger transmission of stored I/O operations to storage devices of the storage system for processing,

wherein if the cache manager identifies cached I/O operations that are directed along signaling pathways that share a common device, the cache manager is operable to interleave other I/O operations between the identified I/O operations,

wherein the other I/O operations utilize signaling pathways that do not share the common device.

2. The storage controller of claim 1 , wherein:

if the cache manager identifies cached I/O operations that are directed along signaling pathways that share a common device, the cache manager is operable to alter one of the identified I/O operations to direct it along a new signaling pathway that does not share a common device.

3. The storage controller of claim 1 , wherein:

the cache manager is distinct from the SSD and any controller internal to the SSD.

4. The storage controller of claim 1 , wherein:

the storage devices implement a striped Redundant Array of Independent Disks (RAID) volume, and

the cache manager is further operable to write each received I/O operation to the cache as one or more full stripes of RAID data.

5. The storage controller of claim 4 , wherein:

the cache memory comprises multiple SSDs, and

the cache manager is further operable to write each block of the stripe to a different SSD.

6. The storage controller of claim 1 , wherein:

the cache comprises a Single-Level Cell (SLC) SSD and a Multi-Level Cell (MLC) SSD, and

the cache manager is further operable to review the received I/O operation to determine whether the I/O operation is a write operation, to store the I/O operation in the MLC SSD if the I/O operation is not a write operation, and to store the I/O operation in the SLC SSD if the I/O operation is a write operation in order to increase the operational lifetime of the MLC SSD.

7. The storage controller of claim 1 , wherein:

the cache comprises multiple SSDs, and

the cache manager is further operable to determine, while operating, that the number of SSDs implementing the cache has changed, and to update the determined set of physical locations to reflect the change.

8. A method for operating a storage controller of a storage system, the method comprising:

receiving Input/Output (I/O) operations from a host computer at a storage controller that includes a cache memory that comprises a Solid State Drive (SSD);

determining physical locations that are unused in the cache memory, via a cache manager of the storage controller;

identifying an unused location that was written to a longer period of time ago than other unused locations;

storing a received I/O operation in the identified physical location;

transmitting the stored I/O operation from the storage controller to a storage device of the storage system;

identifying cached I/O operations that are directed along signaling pathways that share a common device; and

interleaving other I/O operations between the identified I/O operations, wherein the other I/O operations utilize signaling pathways that do not share the common device.

9. The method of claim 8 , further comprising:

altering one of the identified I/O operations to direct it along a new signaling pathway that does not share a common device.

10. The method of claim 8 , further comprising:

the cache manager is distinct from the SSD and any controller internal to the SSD.

11. The method of claim 8 , wherein:

the storage devices implement a striped Redundant Array of Independent Disks (RAID) volume, and the method further comprises:

writing each received I/O operation to the cache as one or more full stripes of RAID data.

12. The method of claim 11 , wherein:

the cache memory comprises multiple SSDs, and the method further comprises:

writing each block of the stripe to a different SSD.

13. The method of claim 8 , wherein:

the cache comprises a Single-Level Cell (SLC) SSD and a Multi-Level Cell (MLC) SSD, and the method further comprises:

reviewing the received I/O operation to determine whether the I/O operation is a write operation;

storing the I/O operation in the MLC SSD if the I/O operation is not a write operation; and

storing the I/O operation in the SLC SSD if the I/O operation is a write operation in order to increase the operational lifetime of the MLC SSD.

14. The method of claim 8 , wherein:

the cache comprises multiple SSDs, and the method further comprises:

determining, while actively operating the storage controller, that the number of SSDs implementing the cache has changed; and

updating the determined set of physical locations to reflect the change.

15. A non-transitory computer readable medium embodying programmed instructions which, when executed by a processor, are operable for performing a method comprising:

receiving Input/Output (I/O) operations from a host computer at a storage controller that includes a cache memory that comprises a Solid State Drive (SSD);

determining physical locations that are unused in the cache memory, via a cache manager of the storage controller; identifying an unused location that was written to a longer period of time ago than other unused locations;

storing a received I/O operation in the identified physical location;

transmitting the stored I/O operation from the storage controller to a storage device of the storage system;

identifying cached I/O operations that are directed along signaling pathways that share a common device; and

interleaving other I/O operations between the identified I/O operations, wherein the other I/O operations utilize signaling pathways that do not share the common device.

16. The medium of claim 15 , the method further comprising:

altering one of the identified I/O operations to direct it along a new signaling pathway that does not share a common device.

17. The medium of claim 15 , the method further comprising:

the cache manager is distinct from the SSD and any controller internal to the SSD.

18. The medium of claim 15 , wherein:

the storage devices implement a striped Redundant Array of Independent Disks (RAID) volume, and the method further comprises:

writing each received I/O operation to the cache as one or more full stripes of RAID data.

19. The medium of claim 18 , wherein:

the cache memory comprises multiple SSDs, and the method further comprises:

writing each block of the stripe to a different SSD.

20. The medium of claim 15 , wherein:

the cache comprises a Single-Level Cell (SLC) SSD and a Multi-Level Cell (MLC) SSD, and the method further comprises:

reviewing the received I/O operation to determine whether the I/O operation is a write operation;

storing the I/O operation in the MLC SSD if the I/O operation is not a write operation; and

storing the I/O operation in the SLC SSD if the I/O operation is a write operation in order to increase the operational lifetime of the MLC SSD.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 036722/0718 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2015
From: MAHARANA, PARAG R; SAMPATHKUMAR, KISHORE K
To: LSI CORPORATION
Reel/Frame 036048/0614 →
Continuity (2)
Continuation 13766985 · Feb 14, 2013
Related Publication 20150378947A1 · Dec 31, 2015