IP Library Granted Patent US 10,664,166
Granted Patent B2
US 10,664,166 · App. 14/795,571 · Granted May 26, 2020

Application-transparent hybridized caching for high-performance storage

Inventors: Kushagra Vaid (Sammamish, WA); Sompong Paul Olarig (Pleasanton, CA)
Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
G06F3/061G06F3/0655G06F3/0685G06F3/0688G06F12/0246G06F12/0871G06F12/0893G11C7/1072G11C11/40615G06F9/4401G06F2212/1016G06F2212/217G06F2212/2146G06F2212/225G06F2212/312G11C16/102
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Quick Facts
Patent No.
US 10,664,166
App. No.
14/795,571
Granted
May 26, 2020
Kind
B2
Abstract

Systems, apparatus, and computer-implemented methods are provided for the hybridization of cache memory utilizing both magnetic and solid-state memory media. A solid-state cache controller apparatus can be coupled to a host computing system to maximize efficiency of the system in a manner that is transparent to the high-level applications using the system. The apparatus includes an associative memory component and a solid-state cache control component. Solid-state memory is configured to store data blocks of host read operations. If a host-read operation is requested, the controller communicates with a solid-state cache memory controller to determine whether a tag array data structure indicates a cached copy of the requested data block is available in solid-state memory.

Claims (34)

1. A computer-implemented method for initializing a system using a hybridized caching system, the method comprising:

beginning a disk discovery event as a result of a boot up or hot-plug;

detecting a presence or an absence of at least one solid-state drive;

when the at least one solid-state drive is detected;

determining whether a solid-state cache controller is supported by the system; and

when the solid-state cache controller is supported, initializing a plurality of cache tags in a cache tag array of the at least one solid-state drive, wherein the cache tag array is a complete proxy for every address in one or more hard disk drives.

2. The method of claim 1 , wherein the disk discovery event is one of ATA, SATA, SCSI, Fibre Channel, and SAS protocols.

3. The method of claim 1 , wherein the solid-state cache controller is a separate discoverable component by a RAID controller.

4. The method of claim 1 , wherein the at least one solid-state drive is located on a ROC controller.

5. The method of claim 1 , wherein the at least one solid-state drive is a flash based solid-state drive.

6. The method of claim 1 , wherein the solid-state cache controller is one of an external controller communicating with a storage controller, an embedded component within the storage controller, or a controller within a plurality of controllers manipulated by a centralized controller.

7. A solid-state cache controller apparatus coupled to a host computing system, the apparatus comprising:

a solid-state cache control component that begins a disk discovery event as a result of a boot up or hot-plug to detect a presence or an absence of at least one solid-state drive;

one or more hard disk drives that are accessed when the presence of the at least one solid-state drive is not supported; and

an associative memory component that initializes a plurality of cache tags in a cache tag array when the presence of the at least one solid-state drive is supported, wherein the cache tag array is a complete proxy for every address in the one or more hard disk drives, wherein a number of cache tags in the cache tag array of the at least one solid-state drive is determined based on a block size of the at least one solid-state drive.

8. The solid-state cache controller apparatus of claim 7 , wherein the solid-state cache control component detects the presence or the absence of the at least one solid-state drive by one of an ATA protocol, a SATA protocol, a SCSI protocol, a Fibre Channel protocol, or a SAS protocol.

9. The solid-state cache controller apparatus of claim 8 , wherein the solid-state cache control component further determines a cache store and persistent store hierarchy through one of the ATA protocol, the SATA protocol, the SCSI protocol, the Fibre Channel protocol, or the SAS protocol.

10. The solid-state cache controller apparatus of claim 7 , wherein the solid-state cache control component is a separate discoverable component by a RAID controller.

11. The solid-state cache controller apparatus of claim 7 , wherein the solid-state cache controller apparatus further comprises a removable solid state cache.

12. The solid-state cache controller apparatus of claim 7 , wherein the associative memory component is one of static random access memory (SRAM) or dynamic random access memory (DRAM).

13. The solid-state cache controller apparatus of claim 7 , wherein the at least one solid-state drive is located remotely from the solid-state cache control component.

14. The solid-state cache controller apparatus of claim 7 , wherein one or more additional solid-state drives can be added without disruption to the host computing system.

15. A solid-state cache controller apparatus coupled to a host computing system, the apparatus comprising:

a solid-state cache control component located on a RAID on Chip (ROC) controller, wherein the solid-state cache control component begins a disk discovery event as a result of a boot up or hot-plug and to detect a presence or an absence of at least one solid-state drive;

one or more hard disk drives that are accessed when the presence of the at least one solid-state drive is not supported; and

an associative memory component that initializes a plurality of cache tags in a cache tag array when the presence of the at least one solid-state drive is supported, wherein the cache tag array is a complete proxy for every address in the one or more hard disk drives.

16. The solid-state cache controller of claim 15 , wherein the solid-state cache controller apparatus detects the presence or the absence of the at least one solid-state drive by one of an ATA protocol, a SATA protocol, a SCSI protocol, a Fibre Channel protocol, and a SAS protocol.

17. The solid-state cache controller apparatus of claim 15 , wherein the solid-state cache controller apparatus further comprises a removable solid state cache.

18. The solid-state cache controller apparatus of claim 15 , wherein the associative memory component is one of static random access memory (SRAM) or dynamic random access memory (DRAM).

19. A solid-state cache controller apparatus coupled to a host computing system, the apparatus comprising:

a solid-state cache control that begins a disk discovery event as a result of a boot up or hot-plug and to detect a presence or an absence of at least one solid-state drive located on a PCI-based adapter;

one or more hard disk drives that are accessed when the presence of the at least one solid-state drive is not supported; and

an associative memory component that initializes a plurality of cache tags in a cache tag array when the presence of the at least one solid-state drive is supported, wherein the cache tag array is a complete proxy for every address in the one or more hard disk drives, wherein a number of cache tags in the cache tag array of the at least one solid-state drive is determined based on a block size of the at least one solid-state drive.

20. The solid-state cache controller apparatus of claim 19 , wherein the solid-state cache controller apparatus further comprises a removable solid state cache.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2017
From: VAID, KUSHAGRA; OLARIG, SOMPONG PAUL
To: MICROSOFT CORPORATION
Reel/Frame 042131/0196 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2017
From: MICROSOFT CORPORATION
To: MICROSOFT TECHNOLOGY LICENSING, LLC
Reel/Frame 042131/0278 →
Continuity (4)
Division 13618851 · Sep 14, 2012
Continuation 12695552 · Jan 28, 2010
Provisional Application 61632416 · Jun 15, 2009
Related Publication 20150309729A1 · Oct 29, 2015