Manufacturing method of thin film transistor display panel
View Patent ↗Provided is a manufacturing method of a thin film transistor array panel including: formation of a gate line including a gate electrode on a substrate; formation of sequentially a gate insulating layer, an active layer, a data metal layer, and a photoresist etching mask pattern on the gate line; etching the data metal layer with the same shape as the photoresist etching mask pattern; etching the active layer by using the photoresist etching mask pattern; formation of a data line including a source electrode and a drain electrode for completing a channel region on the active layer; and formation of a pixel electrode exposing the drain electrode and electrically connected with the drain electrode, in which in the etching of the active layer, a dry-etch process is performed by using gas including at least one of NF3 and H2.
1. A manufacturing method of a thin film transistor array panel, comprising
forming a gate line including a gate electrode on a substrate;
forming sequentially a gate insulating layer, an active layer, a data metal layer, and a photoresist etching mask pattern on the gate line;
etching the data metal layer with the same shape as the photoresist etching mask pattern;
etching the active layer by using the photoresist etching mask pattern by a dry-etch process performed by using gas including at least one of NF 3 and H 2 while forming a silicon compound on an etch surface of the data metal layer by the dry-etch process;
forming a data line including a source electrode and a drain electrode for completing a channel region on the active layer; and
forming a pixel electrode exposing the drain electrode and electrically connected with the drain electrode.
2. The manufacturing method of claim 1 , wherein during the formation of the data line, the silicon compound formed on the etch surface of the data metal layer prevents the etch surface of the data metal layer from being etched.
3. The manufacturing method of claim 1 , wherein the formation of the data line further includes
exposing a part of the data metal layer by etching the photoresist etching mask pattern with a predetermined thickness through ashing; and
forming a source electrode and a drain electrode for completing the channel region of the thin film transistor by etching the exposed data metal layer.
4. The manufacturing method of claim 3 , wherein the formation of the data line is performed by a wet etching process with respect to the data metal layer.
5. The manufacturing method of claim 3 , wherein at least one of low pressure and high bias power satisfies ashing condition.
6. The manufacturing method of claim 3 , wherein the forming of the active layer comprises:
laminating an intrinsic amorphous silicon layer on the gate insulating layer; and
laminating an impurity doped amorphous silicon layer on the intrinsic amorphous silicon layer.
7. The manufacturing method of claim 6 , wherein the formation of the data line further includes
etching the impurity doped amorphous silicon layer exposed between the source electrode and the drain electrode of the thin film transistor.
8. The manufacturing method of claim 7 , wherein the etching of the impurity doped amorphous silicon layer is performed by a wet etching process.
9. The manufacturing method of claim 7 , wherein during the etching of the impurity doped amorphous silicon layer, the silicon compound formed on the etch surface of the data metal layer is etched.