Integrated device having multiple transistors

1. An integrated device comprising:

a semiconductor well formed in an epitaxial layer, wherein said epitaxial layer comprises a first type of semiconductor, and said semiconductor well comprises a second type of semiconductor that is different from said first type of semiconductor;

a first guard ring formed in said epitaxial layer and surrounding said semiconductor well, wherein said first guard ring comprises said second type of semiconductor;

an insulating layer formed atop said first guard ring; and

a plurality of gate electrodes formed on a top surface of said insulating layer, overlapping said first guard ring and surrounding said semiconductor well,

wherein said gate electrodes comprise a first gate electrode and a second gate electrode separated by a gap, wherein said first gate electrode comprises a first side wall above said first guard ring and facing said gap, wherein said second gate electrode comprises a second side wall above said first guard ring and facing said gap, wherein said gap is formed between said first and second side walls above said first guard ring, wherein said gap is shaped so that a first intersecting line between said top surface and said first side wall partially overlaps a first area of said top surface above said first guard ring, and wherein said first area is defined by a second intersecting line between said top surface and said second side wall and by a straight line through said gap and between a first point of said second intersecting line and a second point of said second intersecting line.

2. The integrated device as claimed in claim 1 , wherein said gate electrodes comprise a plurality of transistors, wherein said transistors have a common drain region and a common source region.

3. The integrated device as claimed in claim 2 , wherein said transistors comprise an OR gate.

4. The integrated device as claimed in claim 2 , wherein said common drain region comprises a part of said epitaxial layer, and wherein said common source region is formed in said semiconductor well and comprises said first type of semiconductor.

5. The integrated device as claimed in claim 1 , wherein said first gate electrode, said insulating layer, and said first guard ring comprise a first capacitor, and wherein said second gate electrode, said insulating layer, and said first guard ring comprise a second capacitor.

6. The integrated device as claimed in claim 5 , wherein when a voltage is applied to said integrated device to cause an electric field extending from said semiconductor well to said first guard ring, said first and second capacitors terminate the part of said electric field that is in an area under said gap.

7. The integrated device as claimed in claim 6 , wherein said first and second capacitors are operable for holding charges thereby terminating said electric field.

8. The integrated device as claimed in claim 1 , wherein said first type of semiconductor comprises n-type semiconductor, and said second type of semiconductor comprises p-type semiconductor.

9. The integrated device as claimed in claim 1 , further comprising:

a trench-like structure surrounding said semiconductor well; and

a second guard ring formed on a side wall of said trench-like structure and surrounding said semiconductor well, wherein said insulating layer is formed atop said second guard ring, and wherein said first and second gate electrodes are formed on said top surface of said insulating layer overlapping said second guard ring.

10. The integrated device as claimed in claim 9 , wherein said first gate electrode further comprises a third side wall above said second guard ring and facing said gap, wherein said second gate electrode further comprises a fourth side wall above said second guard ring and facing said gap, wherein said gap is also formed between said third and fourth side walls above said second guard ring, wherein said gap is also shaped so that a third intersecting line between said top surface and one of said third and fourth side walls partially overlaps a second area of said top surface above said second guard ring, and wherein said second area is defined by a fourth intersecting line between said top surface and the other one of said third and fourth side walls and by a straight line between a third point of said fourth intersecting line and a fourth point of said fourth intersecting line.

11. An integrated device comprising:

a plurality of transistors comprising a common source region and a common drain region, and comprising a plurality of gate electrodes formed on a top surface of an insulating layer and surrounding said common source region, wherein said common drain and common source regions comprise a first type of semiconductor;

a first guard ring formed beneath said insulating layer, overlapped by said gate electrodes and surrounding said common source region, wherein said first guard ring comprises a second type of semiconductor that is different from said first type of semiconductor,

wherein said gate electrodes comprise a first gate electrode and a second gate electrode separated by a gap, wherein said first gate electrode comprises a first side wall above said first guard ring and facing said gap, wherein said second gate electrode comprises a second side wall above said first guard ring and facing said gap, wherein said gap is formed between said first and second side walls above said first guard ring, wherein said gap is shaped so that a first intersecting line between said top surface and said first side wall partially overlaps a first area of said top surface above said first guard ring, and wherein said first area is defined by a second intersecting line between said top surface and said second side wall and by a straight line between a first point of said second intersecting line and a second point of said second intersecting line.

12. The integrated device as claimed in claim 11 , wherein said common drain region comprises a part of a semiconductor substrate on which said transistors are formed, wherein said common source region is formed in a semiconductor well surrounded by said first guard ring, and wherein said semiconductor well comprises said second type of semiconductor.

13. The integrated device as claimed in claim 11 , wherein said transistors comprise an OR gate.

14. The integrated device as claimed in claim 11 , wherein said first gate electrode, said insulating layer, and said first guard ring comprise a first capacitor, and wherein said second gate electrode, said insulating layer, and said first guard ring comprise a second capacitor.

15. The integrated device as claimed in claim 14 , further comprising a semiconductor well formed between said common source region and said common drain region and surrounded by said first guard ring, wherein when a voltage is applied to said integrated device to cause an electric field extending from said semiconductor well to said first guard ring, said first and second capacitors terminate the part of said electric field that is in an area under said gap.

16. The integrated device as claimed in claim 15 , wherein said first and second capacitors are operable for holding charges thereby terminating said electric field.

17. The integrated device as claimed in claim 11 , wherein said first type of semiconductor comprises n-type semiconductor, and said second type of semiconductor comprises p-type semiconductor.

18. The integrated device as claimed in claim 11 , further comprising:

a trench-like structure surrounding said common source region; and

a second guard ring formed on a side wall of said trench-like structure and surrounding said common source region, wherein said insulating layer is formed atop said second guard ring, and wherein said first and second gate electrodes are formed on said top surface of said insulating layer overlapping said second guard ring.

19. The integrated device as claimed in claim 11 , wherein said first gate electrode further comprises a third side wall above said second guard ring and facing said gap, wherein said second gate electrode further comprises a fourth side wall above said second guard ring and facing said gap, wherein said gap is also formed between said third and fourth side walls above said second guard ring, wherein said gap is also shaped so that a third intersecting line between said top surface and one of said third and fourth side walls partially overlaps a second area of said top surface above said second guard ring, and wherein said second area is defined by a fourth intersecting line between said top surface and the other one of said third and fourth side walls and by a straight line between a third point of said fourth intersecting line and a fourth point of said fourth intersecting line.