Controlling on-state current for two-terminal memory
Provision of fabrication, construction, and/or assembly of a memory device including a two-terminal memory portion is described herein. The two-terminal memory device fabrication can provide enhanced capabilities in connection with precisely tuning on-state current over a greater possible range.
1. A method for fabricating a memory device, comprising:
forming a two-terminal memory layer above a substrate layer;
including in the two-terminal memory layer an ohmic contact layer above the substrate layer, a resistive layer above the ohmic contact layer, a resistive switching material (RSM) layer above the resistive layer, and an active metal layer above the RSM layer;
including a first semiconductor material layer in an amorphous phase in the resistive layer; and
including a second semiconductor material layer in a polycrystalline phase in the resistive layer situated above the first semiconductor layer.
2. The method of claim 1 , further comprising forming the second semiconductor material layer from a p-type conductive semiconductor material comprising polycrystalline silicon germanium (SiGe).
3. The method of claim 1 , further comprising forming the second semiconductor material with a resistivity in a range of about 0.001 ohm-centimeters to about 0.5 ohm-centimeters.
4. The method of claim 3 , further comprising forming the second semiconductor material with a thickness in a range of about 5 nanometers to about 50 nanometers.
5. The method of claim 1 , further comprising receiving a resistance data associated with a target resistance for the resistive layer.
6. The method of claim 5 , further comprising determining from the resistance data a thickness value for the resistive layer associated with the target resistance.
7. The method of claim 6 , further comprising forming the second semiconductor material layer with a thickness equal to the thickness value.
8. The method of claim 1 , further comprising forming the RSM layer from an undoped amorphous silicon material or a silicon sub-oxide material.
9. The method of claim 1 , further comprising forming the RSM layer from a titanium oxide material.
10. The method of claim 1 , further comprising forming the RSM layer from a silicon oxide layer.
11. The method of claim 1 , further comprising forming the RSM layer from a first sub-layer comprising a titanium oxide material, and from a second sub-layer adjacent to the first sub-layer comprising a silicon sub-oxide material.
12. The method of claim 1 , further comprising forming a barrier layer adjacent to the RSM layer and the active metal layer, wherein the barrier layer comprises at least one of titanium, titanium oxide, tungsten, or titanium nitride.
13. The method of claim 1 , further comprising: forming the first semiconductor material and the second semiconductor material at a temperature that is within a thermal budget of a complementary metal oxide semiconductor device formed at least in part within the substrate layer.
14. The method of claim 13 , further comprising forming the first semiconductor material and the second semiconductor material at a temperature equal to or below about 450° C.
15. The method of claim 1 , further comprising forming the second semiconductor material in physical contact with the RSM layer.
16. A method of fabricating a non-volatile memory, comprising:
providing a substrate having a complementary metal oxide semiconductor (CMOS) device within the substrate;
forming a dielectric layer over the substrate;
forming a first metal layer over the dielectric layer;
forming a resistive layer over the first metal layer, wherein forming the resistive layer further comprises forming an amorphous phase material overlying the first metal layer and forming a polycrystalline phase material overlying the amorphous phase material;
forming a resistive switching material (RSM) layer over the resistive layer; and
forming an active metal layer over the RSM layer.
17. The method of claim 16 , further comprising forming the non-volatile memory within a thermal budget of the CMOS device.
18. The method of claim 16 , further comprising forming the RSM layer adjacent to the crystalline phase material.
19. The method of claim 16 , wherein forming the resistive layer further comprises forming the amorphous phase material and the polycrystalline phase material, respectively, as a p-type semiconductor material.
20. The method of claim 16 , further comprising at least one of:
forming the amorphous phase material with a resistivity within a range between about 5 ohm-centimeters and about 50 ohm-centimeters; or
forming the polycrystalline phase material with a second resistivity within a second range between about 0.001 ohm-centimeters and about 0.5 ohm-centimeters.