Offset correction for sense amplifier
View Patent ↗The present invention is directed to data communication. More specifically, embodiments of the present invention provide an offset correction technique for a SERDES system. A CTLE module for receiving input data signal is set to an isolation mode, and one or more sense amplifiers perform data sampling asynchronously during the isolation mode. During the isolation mode, CLTE(s) that are not directly connected to the sense amplifiers are shut. Data sampled during the isolation mode are used to determine an offset value that is later used in normal operation of the SERDES system. There are other embodiments as well.
1. A method for providing offset correction, the method comprising:
processing input signals by an equalizer module, the equalizer module comprising a first Continuous Time Linear Equalizer (CTLE) and a second CTLE, the second CTLE being coupled to a first sense amplifier, the input signals being associated with a first sampling rate;
initiating an isolation mode by shutting off at least the first CTLE and operating the second CTLE in a common mode;
generating a first equalizer signal by the second CTLE in the isolation mode, the first equalizer signal comprising a noise associated with a capacitive coupling effect;
providing a predetermined number of offset samples by sampling the first equalizer signal by the first sense amplifier at a second sampling rate, the second sampling rate being different from the first sampling rate;
determining a digital offset value based on the predetermined number of offset samples;
initiating an operational mode by setting at least the first CTLE and the second CTLE to an operation mode;
providing a second equalizer signal from the second CTLE, the second equalizer signal being based on output from the first CTLE in the operation mode;
generating an analog offset signal using at least the digital offset value; and
performing sampling by at least the first sense amplifier using at least the second equalizer signal and the analog offset signal at the first sampling rate.
2. The method of claim 1 further comprising converting the digital offset value to the analog offset signal by a Digital to Analog Converter (DAC) module.
3. The method of claim 1 further comprising performing sampling by a second sense amplifier using at least the second equalizer signal and the analog offset signal at the first sampling rate.
4. The method of claim 1 wherein the first sense amplifier comprises a data sense amplifier and an edge sense amplifier.
5. The method of claim 1 further comprising performing early/late detection on data sampled by the first sense amplifier at the first sampling rate.
6. The method of claim 1 wherein the first sense amplifier receives a clock signal.
7. The method of claim 1 further comprising shutting off a third CTLE when operating in the isolation mode.
8. The method of claim 1 wherein the predetermined number of offset samples is stored using at least 32-bits of data.
9. The method of claim 1 wherein the sampling at the second sampling rate by the first sense amplifier is asynchronous.
10. The method of claim 1 wherein the first equalizer signal is characterized by a first swing voltage and the second equalizer signal is characterized by a second swing voltage, the second swing voltage being greater than the first swing voltage.
11. The method of claim 1 wherein the second equalizer signal comprises a positive signal and a negative signal.
12. The method of claim 1 wherein the analog offset signal comprises a positive signal and a negative signal.
13. A Serializer Deserializer (SERDES) device comprising:
an equalizer module comprising a first Continuous Time Linear Equalizer (CTLE) and a second CTLE, an output of the first CTLE being connected to an input of the second CTLE, the second CTLE being configured to generate an equalizer output signal from an input signal, the input signal being characterized by a first sampling frequency;
a digital correction module being configured to determine and provide an offset correction value;
a Digital to Analog Converter (DAC) being configured to generate an offset correction signal, the offset correction signal being determined at an isolation mode;
a first sense amplifier being configured to generate data samples by sampling the equalizer output signal from the second CTLE at the first sampling frequency using the offset correction signal;
a decoder configured to determine relative position of the data samples;
a Phase-Lock Loop (PLL) being configured to provide a clock signal for the first sense amplifier;
wherein during the isolation mode:
the first CTLE is shut and the second CTLE operates in a common mode and generates a second equalizer output signal;
the first sense amplifier generates a predetermined number of samples at a second sampling frequency, the second sampling frequency being different from the first sampling frequency;
the digital correction module determines the offset correction value using the predetermined number of samples.
14. The apparatus of claim 13 further comprising a second sense amplifier, wherein the second sense amplifier is an edge sense amplifier.
15. The apparatus of claim 13 further comprising a Demultiplexor (DEMUX) for selecting the data samples from the first sense amplifier.
16. The apparatus of claim 13 wherein the equalizer module further comprising a third CTLE, output of the third CTLE being coupled to an input of the first CTLE, the third CTLE being shut during the isolation mode.
17. The apparatus of claim 13 further comprising a second sense amplifier, wherein the first sense amplifier comprises a data sense amplifier and the second sense amplifier comprises an edge amplifier.
18. A Serializer Deserializer (SERDES) device comprising:
an equalizer module comprising a first Continuous Time Linear Equalizer (CTLE) and a second CTLE, an output of the first CTLE being connected to an input of the second CTLE, the second CTLE being configured to generate an equalizer output signal from an input signal, the input signal being characterized by a first sampling frequency;
an offset correction module being configured to generate an offset correction signal;
a first sense amplifier being configured to generate data samples by sampling the equalizer output signal from the second CTLE at the first sampling frequency using the offset correction signal;
a second sense amplifier being configured to process the equalizer output signal at the first sampling frequency;
a decoder configured to determine relative position of the data samples;
a Phase-Lock Loop (PLL) being configured to provide a clock signal for the first sense amplifier;
wherein during an isolation mode:
the first CTLE is shut and the second CTLE operates in a common mode and generates a second equalizer output signal;
the first sense amplifier generates a predetermined number of samples at a second sampling frequency, the second sampling frequency being different from the first sampling frequency;
the offset correction module determines the offset correction signal using at least the predetermined number of samples.
19. The device of claim 18 wherein the offset correction module comprises a digital correction module.
20. The device of claim 18 wherein the offset correction module comprises a Digital to Analog Converter (DAC).