In-cycle resource sharing for high-level synthesis of microprocessors

1. A method of preparing a digital electronic integrated circuit implementing a plurality of logical operations and a plurality of branch logic blocks, said method comprising:

acquiring from a gate array or from a machine readable storage medium an input design structure representing a physical structure of said plurality of logical operations and said plurality of branch logic blocks in said digital electronic integrated circuit;

constructing a graph having a plurality of nodes representing said plurality of logical operations and a plurality of edges connecting those of said plurality of nodes which do not conflict;

assigning to each of said edges a weight comprising a bit width difference between end nodes of each of said edges;

enumerating weighted cliques each comprising at least two of said nodes representing respective ones of the logical operations that can share a same clock cycle of said digital electronic integrated circuit;

generating a plurality of multiplexer-operation groups by replacing each of said weighted cliques with a single one of said logical operations and a multiplexer, such that each logical operation in one of said multiplexer-operation groups can be shared among at least two of said plurality of branch logic blocks within a same clock cycle of said digital electronic integrated circuit; and

configuring an output design structure incorporating said multiplexer-operation groups for fabricating said digital electronic integrated circuit.

2. The method of claim 1 , wherein said assigned weights have values no less than zero, and wherein said enumerated weighted cliques comprise minimum weighted cliques.

3. The method of claim 1 , wherein said assigned weights have values no greater than zero, and wherein said enumerated weighted cliques comprise maximum weighted cliques.

4. The method of claim 3 , wherein said constructing of said graph comprises:

constructing a preliminary graph having said plurality of nodes representing said plurality of logical operations and a plurality of preliminary edges connecting all of said nodes; and

based on an analysis of said plurality of branch logic blocks, removing from said preliminary graph those of said plurality of preliminary edges connecting those of said plurality of nodes which do conflict, to leave said edges connecting those of said plurality of nodes which do not conflict.

5. The method of claim 4 , further comprising:

updating a control data flow graph representing said digital electronic integrated circuit based on said enumerated maximum weighted cliques;

computing timing impact of said updated control data flow graph; and

eliminating selected sharing of said logical operations if said timing impact indicates excessive timing degradation.

6. The method of claim 5 , wherein said enumerating of said maximum weighted cliques is carried out via a modified Bron-Kerbosch technique.

7. The method of claim 6 , wherein said logical operations each comprise one of addition, subtraction, multiplication, division, and shift.

8. The method of claim 7 , further comprising fabricating said integrated circuit with said plurality of multiplexer-operation groups.

9. An apparatus for preparing a digital electronic integrated circuit implementing a plurality of logical operations and a plurality of branch logic blocks, said apparatus comprising:

a memory;

at least one processor, coupled to said memory; and

a non-transitory computer readable medium comprising computer executable instructions which when loaded into said memory configure said at least one processor to:

acquire from a gate array or from a machine-readable storage medium an input design structure that represents a physical structure of said plurality of logical operations and said plurality of branch logic blocks in said digital electronic integrated circuit;

construct, in said memory, a graph of said input design structure, said graph having a plurality of nodes representing said plurality of logical operations and a plurality of edges connecting those of said plurality of nodes which do not conflict;

assign, in said memory, to each of said edges a weight comprising a bit width difference between end nodes of each of said edges;

enumerate, in said memory, weighted cliques each comprising at least two of said nodes representing respective ones of the logical operations that can share a same clock cycle of said digital electronic integrated circuit;

generate, in said memory, a plurality of multiplexer-operation groups by replacing each of said weighted cliques with a single one of said logical operations and a multiplexer, such that each logical operation in one of said multiplexer-operation groups can be shared within a same clock cycle of said digital electronic integrated circuit; and

configure an output design structure incorporating said multiplexer-operation groups in an integrated circuit manufacturing machine for fabricating said digital electronic integrated circuit.

10. The apparatus of claim 9 , wherein said assigned weights have values no less than zero, and wherein said enumerated weighted cliques comprise minimum weighted cliques.

11. The apparatus of claim 9 , wherein said assigned weights have values no greater than zero, and wherein said enumerated weighted cliques comprise maximum weighted cliques.

12. The apparatus of claim 11 , wherein said constructing of said graph comprises:

constructing a preliminary graph having said plurality of nodes representing said plurality of logical operations and a plurality of preliminary edges connecting all of said nodes; and

based on an analysis of said plurality of branch logic blocks, removing from said preliminary graph those of said plurality of preliminary edges connecting those of said plurality of nodes which do conflict, to leave said edges connecting those of said plurality of nodes which do not conflict.

13. The apparatus of claim 12 , wherein said instructions further configure said at least one processor to:

update a control data flow graph representing said digital electronic integrated circuit based on said enumerated maximum weighted cliques;

compute timing impact of said updated control data flow graph; and

eliminate selected sharing of said logical operations if said timing impact indicates excessive timing degradation.

14. The apparatus of claim 13 , wherein said enumerating of said maximum weighted cliques is carried out via a modified Bron-Kerbosch technique.

15. The apparatus of claim 14 , wherein said logical operations each comprise one of addition, subtraction, multiplication, division, and shift.

16. A non-transitory computer readable medium comprising computer executable instructions which when executed by a computer cause the computer to perform a method of preparing a digital electronic integrated circuit implementing a plurality of logical operations and a plurality of branch logic blocks, said method comprising:

constructing, in a memory coupled in communication with a processor of said computer, a graph having a plurality of nodes representing said plurality of logical operations and a plurality of edges connecting those of said plurality of nodes which do not conflict;

assigning to each of said edges, in said memory, a weight comprising a bit width difference between end nodes of each of said edges;

enumerating, in said memory, weighted cliques each comprising at least two of said nodes representing respective ones of the logical operations that can share a same clock cycle of said digital electronic integrated circuit;

generating, in said memory, a plurality of multiplexer-operation groups by replacing each of said weighted cliques with a single one of said logical operations and a multiplexer, such that each logical operation in one of said multiplexer-operation groups can be shared within a same clock cycle of said digital electronic integrated circuit; and

facilitating manufacturing or programming a functionally equivalent representation of said digital electronic integrated circuit including said multiplexer-operation groups.

17. The non-transitory computer readable medium of claim 16 , wherein said assigned weights have values no less than zero, and wherein said enumerated weighted cliques comprise minimum weighted cliques.

18. The non-transitory computer readable medium of claim 16 , wherein said assigned weights have values no greater than zero, and wherein said enumerated weighted cliques comprise maximum weighted cliques.

19. The non-transitory computer readable medium of claim 18 , wherein said constructing of said graph comprises:

constructing a preliminary graph having said plurality of nodes representing said plurality of logical operations and a plurality of preliminary edges connecting all of said nodes; and

based on an analysis of said plurality of branch logic blocks, removing from said preliminary graph those of said plurality of preliminary edges connecting those of said plurality of nodes which do conflict, to leave said edges connecting those of said plurality of nodes which do not conflict.

20. The non-transitory computer readable medium of claim 19 , further comprising computer executable instructions which when executed by said computer cause the computer to perform further method steps of:

updating a control data flow graph representing said digital electronic integrated circuit based on said enumerated maximum weighted cliques;

computing timing impact of said updated control data flow graph; and

eliminating selected sharing of said logical operations if said timing impact indicates excessive timing degradation.