Semiconductor device having a plurality of transistors connected in parallel
A semiconductor device SD includes a substrate SUB, a plurality of gate electrodes GE, a gate pad GEP, and gate interconnects GINC. The plurality of gate electrodes GE are formed in the substrate SUB, and extend electrically in parallel to each other. The gate pad GEP is formed in a region different from that in which the plurality of gate electrodes GE are formed in the substrate SUB. Each of a plurality of gate interconnects GINC connects the plurality of gate electrodes GE to the gate pad GEP.
1. A semiconductor device comprising:
a substrate;
a plurality of gate electrodes, formed in the substrate, which extend in parallel to each other;
a first gate interconnect comprising a plurality of connecting portions connected to each of the plurality of gate electrodes;
a gate terminal which is formed in a place different from that in which the plurality of gate electrodes and the first gate interconnect are formed in the substrate; and
a second gate interconnect that connects the gate terminal and the first gate interconnect to each other,
wherein a resistance value of the first gate interconnect per unit length is larger than a resistance value of the second gate interconnect per unit length,
wherein the first gate interconnect and the second gate interconnect have a configuration in which a first layer and a second layer are laminated, and
wherein a width of the second layer in the first gate interconnect is smaller than a width of the second layer in the second gate interconnect.
2. The semiconductor device according to claim 1 , wherein both the second layer in the first gate interconnect and the second layer in the second gate interconnect are divided into a plurality in a width direction,
all widths of the second layers after division are equal to each other, and
a number of the second layers in the first gate interconnect is smaller than a number of the second layers in the second gate interconnect.
3. The semiconductor device according to claim 1 , further comprising an insulating interlayer which is formed over the first layer,
wherein the second layer is formed on the insulating interlayer, and
the second gate interconnect further includes a third layer, buried in the insulating interlayer, which connects the first layer and the second layer to each other.
4. The semiconductor device according to claim 1 , further comprising a plurality of trenches, formed in the substrate, which extend in parallel to each other,
wherein the gate electrodes are formed in the plurality of trenches.