Method and apparatus for obtaining a maximally compressed verification test set

1. A computer-implemented method of improving hardware verification coverage of a microprocessor design by minimizing a test set for optimal coverage, said method comprising:

generating, via a processor, a first test set which is both an empty and minimal test set;

generating, via the processor, a second test set with a predetermined number of tests;

comparing the predetermined number of tests in the second test set with a threshold;

conducting an optimization process in response to the predetermined number of tests in the second test set being greater than the threshold, the optimization process comprising:

partitioning, via the processor, the second test set into a first test subset and a second test subset based on a preselected percentage;

merging, via the processor, the first test subset with the first test set to form a merged list of test sets; and

identifying, via an analyzer, tests in the second test subset that provide unique coverage compared to the merged list of test sets; and

performing hardware verification of the microprocessor design using the identified tests.

2. The computer-implemented method of claim 1 , further comprising:

comparing, via the analyzer, the second test subset to the merged list of test sets to identify an additional test set which provides coverage not already covered by the merged list of test sets when the predetermined number of tests in the second test set is greater than the threshold.

3. The computer-implemented method of claim 2 , further comprising:

adding, via the processor, the additional test set which provides the coverage not already covered to the first empty minimal test set when the predetermined number of tests in the second test set is greater than the threshold.

4. The computer-implemented method of claim 3 , further comprising:

re-defining, via the processor, the first empty minimal test set by iterations of prior steps for adding test sets for providing additional coverage not already covered when the predetermined number of tests in the second test set is greater than the threshold.

5. The computer-implemented method of claim 4 , further comprising:

terminating, via the processor, the iterations of the prior steps for providing additional coverage not already covered when a number of tests in the test set list is either nearly equal to or less than the threshold.

6. The computer-implemented method of claim 2 , further comprising:

identifying, via the analyzer, the unique coverage test by partitioning the second test subset and further ranking each of the partitions of the second test subset with respect to the merged list of test sets when the predetermined number of tests in the second test set is less than the threshold.

7. An apparatus having improved hardware verification coverage of a microprocessor design by minimizing a test set for optimal coverage, said apparatus comprising:

a generator for generating a first test set wherein the first test set is both an empty and minimal test set, and for generating a second test set with a predetermined number of tests;

a processor configured to:

compare the predetermined number of tests in the second test set with a threshold, and

conduct an optimization process in response to the predetermined number of tests in the second test set being greater than the threshold, wherein the optimization process comprises:

partitioning the second test set into a first test subset and a second test subset based on a preselected percentage,

merging the first test subset with the first test set to form a merged list of test sets, and

identifying tests in the second test subset that provide unique coverage compared to the merged list of test sets; and

perform hardware verification of the microprocessor design using the identified tests.

8. The apparatus of claim 7 , further comprising:

an analyzer for comparing the second test subset to the merged list of test sets to identify an additional test set which provides coverage not already covered by the merged list of test sets.

9. The apparatus of claim 8 , further comprising:

a processor for adding additional test set which provide coverage not covered to the first empty minimal test set.

10. The apparatus of claim 9 , further comprising:

a processor for re-defining the first empty minimal test set by repeating iterations of prior steps for adding tests for providing additional coverage not already provided.

11. The apparatus of claim 10 , further comprising:

a processor for terminating the iterations of prior steps when a number of tests in the test set list is nearly equal to or less than the threshold.

12. The apparatus of claim 8 , wherein the unique coverage test is identified by partitioning the second test subset and ranking each of the partitions in the merged list of test sets.

13. A system of improving hardware verification coverage of a microprocessor design by minimizing a test set for optimal coverage, the system comprising:

at least one processor;

at least one computer-readable storage device comprising instructions that when executed cause performance of a method for minimizing a test set for optimal coverage, the method comprising:

generating a first test set wherein the first test set is both an empty and minimal test set;

generating a second test set with a predetermined number of tests;

comparing the predetermined number of tests in the second test set with a threshold;

conducting an optimization process in response to the predetermined number of tests in the second test set being greater than the threshold, wherein the optimization process comprises:

partitioning the second test set into a first test subset and a second test subset based on a preselected percentage;

merging the first test subset with the first test set to form a merged list of test sets; and

identifying tests in the second test subset that provide unique coverage compared to the merged list of test sets; and

performing hardware verification of the microprocessor design using the identified tests.

14. The system of claim 13 , further comprising:

an analysis module for comparing the second test subset to the merged list of test sets to identify an additional test set which provides coverage not already covered by the merged list of test sets.

15. The system of claim 14 , further comprising:

a processor for adding the additional test set which provides the coverage not already covered to the first test set.

16. The system of claim 15 , further comprising:

a processor for re-defining the first empty minimal test set by iterations of repeating the prior steps for adding test sets for providing additional coverage not already provided.

17. The system of claim 16 , further comprising:

a processor for ending the iterations of the prior steps when a number of tests in the test set list is less than the threshold.

18. The system of claim 14 , wherein the unique coverage test is identified by partitioning the second test subset and ranking each of the partitions in the merged list of test sets.