IP Library Granted Patent US 9,444,662
Granted Patent B2
US 9,444,662 · App. 14/802,963 · Granted Sep 13, 2016

Contention avoidance control device and contention avoidance control method for PWM output and A/D conversion, as well as power control system

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Quick Facts
Patent No.
US 9,444,662
App. No.
14/802,963
Granted
Sep 13, 2016
Kind
B2
Abstract

In a contention avoidance control device and a contention avoidance control method for PWM output and A/D conversion, the change timings of PWM outputs are detected, and output of a received A/D conversion trigger to an A/D conversion circuit is inhibited within a predetermined time measured based on the change timings.

Claims (51)

1. A contention avoidance control device for pulse width modulation (PWM) output and analog-to-digital (A/D) conversion, wherein

the contention avoidance control device detects a change timing of each of a plurality of PWM outputs and inhibits an output of a received AD conversion trigger to an A/D converter at least during a predetermined time measured based on each of the change timings.

2. The contention avoidance control device of claim 1 , wherein

after a lapse of the predetermined time, an A/D conversion trigger input received in the predetermined time is output as an A/D conversion trigger output to the A/D converter.

3. The contention avoidance control device of claim 1 , wherein

the predetermined time is arbitrarily set.

4. The contention avoidance control device of claim 1 , wherein

the contention avoidance control device detects the change timing by detecting at least one of a rising edge or a falling edge of the PWM output.

5. The contention avoidance control device of claim 2 , wherein

the A/D conversion trigger input is output as the A/D conversion trigger output in a case where the A/D conversion trigger input is not output after a lapse of an arbitrary time from reception of the A/D conversion trigger input.

6. The contention avoidance control device of claim 2 , wherein

the A/D conversion trigger input is not output when an arbitrary time has elapsed from reception of the A/D conversion trigger input.

7. The contention avoidance control device of claim 2 , wherein

the A/D conversion trigger input is output as the A/D conversion trigger output in a case where the A/D conversion trigger input is not output when the A/D conversion trigger input is counted up to a predetermined number of times within the predetermined time.

8. The contention avoidance control device of claim 2 , wherein

the A/D conversion trigger input is not output in a case where the A/D conversion trigger input is counted up to a predetermined number of times within the predetermined time.

9. The contention avoidance control device of claim 2 , wherein

the A/D conversion trigger input is output as an A/D conversion sample-and-hold control signal to the A/D converter circuit, and

the A/D conversion sample-and-hold control signal is used to extend a sample-and-hold time of the A/D converter circuit for the predetermined time.

10. The contention avoidance control device of claim 1 , wherein

an A/D conversion trigger input received in a predetermined time measured based on each of the change timings is not output.

11. A power control system comprising:

a plurality of converter devices; and

a microcomputer that includes the contention avoidance control device of claim 1 and controls the plurality of converter devices, wherein

the microcomputer controls the plurality of converter devices so as to avoid contention between PWM outputs for controlling the plurality of converter devices and A/D conversion.

12. The power control system of claim 11 , wherein

each of the plurality of converter devices is an inverter or a converter.

13. The power control system of claim 12 , wherein

each of the plurality of converter devices is either the inverter that controls a motor or the converter that controls one of AC to DC conversion, DC to DC conversion, DC to AC conversion, or AC to AC conversion.

14. A contention avoidance control method for avoiding contention between PWM output and A/D conversion, the method comprising:

detecting a change timing of each of a plurality of PWM outputs; and

inhibiting an output of a received A/D conversion trigger to an A/D converter circuit at least during a predetermined time measured based on each of the change timings.

15. The method of claim 14 , further comprising:

outputting an A/D conversion trigger input received in the predetermined time as an A/D conversion trigger output to the A/D converter circuit after a lapse of the predetermined time.

16. The method of claim 14 , wherein

the predetermined time is arbitrarily set.

17. The method of claim 14 , wherein

the change timing is detected by detecting at least one of a rising edge or a falling edge of the PWM output.

18. The method of claim 15 , wherein

the A/D conversion trigger input is output as the A/D conversion trigger output in a case where the A/D conversion trigger input is not output after a lapse of an arbitrary time from reception of the A/D conversion trigger input.

19. The method of claim 15 , wherein

the A/D conversion trigger input is not output when an arbitrary time has elapsed from reception of the A/D conversion trigger input.

20. The method of claim 18 , wherein

the A/D conversion trigger input is not output in a case where a change of the A/D conversion trigger input is counted up to a predetermined number of times within the predetermined time.

21. The method of claim 15 , wherein

the A/D conversion trigger input is output as the A/D conversion trigger output in a case where the A/D conversion trigger input is not output when the A/D conversion trigger input is counted to a predetermined number of times within the predetermined time.

22. The method of claim 19 , wherein

an A/D conversion trigger input received in a predetermined time measured based on each of the change timings is not output.

23. The method of claim 15 , further comprising:

outputting the A/D conversion trigger input as an A/D conversion sample-and-hold control signal to an A/D converter circuit, wherein

the A/D conversion sample-and-hold control signal is used to extend a sample-and-hold time of the A/D converter circuit for the predetermined time.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0870 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 16, 2015
From: IMAMURA, KATSUYUKI; SUGIOKA, TETSURO
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 036334/0509 →