Signal demodulation apparatus and signal demodulation method
View Patent ↗A signal demodulation apparatus includes: a clock generation device arranged to generate a clock signal according to an inputting modulation signal; and a demodulation device arranged to demodulate the inputting modulation signal to generate a demodulation signal according to the clock signal; wherein a signal edge of the clock signal substantially aligns to a turning point of the inputting modulation signal.
1. A signal demodulation apparatus, comprising:
a clock generation device, arranged to generate a clock signal according to an inputting modulation signal; and
a demodulation device, arranged to demodulate the inputting modulation signal to generate a demodulation signal according to the clock signal;
wherein a signal edge of the clock signal substantially aligns to a turning point of the inputting modulation signal;
wherein the clock generation device comprises:
a comparator, having a first input terminal for receiving the inputting modulation signal;
a first transistor, having a first connecting terminal for receiving the inputting modulation signal, a second connecting terminal coupled to a second input terminal of the comparator, and a controlling terminal coupled to an output terminal of the comparator;
a second transistor, having a controlling terminal coupled to the output terminal of the comparator, and a first connecting terminal coupled to a reference voltage;
a resistor, having a first terminal coupled to a second connecting terminal of the second transistor, and a second terminal coupled to the second connecting terminal of the first transistor; and
a capacitor, having a first terminal coupled to the second connecting terminal of the first transistor, and a second terminal coupled to the reference voltage;
wherein the clock signal is a signal on the output terminal of the comparator.
2. The signal demodulation apparatus of claim 1 , wherein the turning point of the inputting modulation signal is a peak or a valley of the inputting modulation signal.
3. The signal demodulation apparatus of claim 1 , wherein the demodulation device comprises:
a sample and hold circuit, arranged to sample the inputting modulation signal to generate an envelope signal by using the clock signal;
a first filter, arranged to filter out a first signal component in the envelope signal to generate a first filtered signal;
a second filter, arranged to filter out a second signal component in the envelope signal from the first filtered signal to generate a second filtered signal; and
a comparator, having a first input terminal for receiving the second filtered signal, a second input terminal for receiving a first reference voltage, and an output terminal for outputting the demodulation signal.
4. The signal demodulation apparatus of claim 3 , wherein the first filter is a high-pass filter arranged to change a DC (Direct current) signal of the envelope signal into the first reference voltage, and to accordingly generate the first filtered signal.
5. The signal demodulation apparatus of claim 3 , wherein the second filter is a low-pass filter arranged to filter out a sampling noise of the envelope signal, and to accordingly generate the second filtered signal.
6. The signal demodulation apparatus of claim 3 , wherein the sample and hold circuit comprises:
a switch, having a first connecting terminal receiving the inputting modulation signal, a controlling terminal receiving the clock signal for selectively coupling the inputting modulation signal to a second connecting terminal of the switch; and
a capacitor, having a first terminal coupled the second connecting terminal of the switch, and a second terminal coupled to a second reference voltage;
wherein the envelope signal is a signal on the first terminal of the capacitor.
7. The signal demodulation apparatus of claim 3 , wherein the first filter comprises:
a capacitor, having a first terminal receiving the envelope signal; and
a resistor, having a first terminal coupled to a second terminal of the capacitor, and a second terminal coupled to the first reference voltage;
wherein the first filtered signal is a signal on the first terminal of the resistor.
8. The signal demodulation apparatus of claim 3 , wherein the second filter comprises:
a first resistor, having a first terminal receiving the first filtered signal;
a first capacitor, having a first terminal coupled to a second terminal of the first resistor, and a second terminal coupled to the first reference voltage;
a second resistor, having a first terminal coupled to the second terminal of the first resistor; and
a second capacitor, having a first terminal coupled to a second terminal of the second resistor, and a second terminal coupled to the first reference voltage;
wherein the second filtered signal is a signal on the first terminal of the second capacitor.
9. The signal demodulation apparatus of claim 1 , wherein the demodulation device comprises:
a sample and hold circuit, arranged to sample the inputting modulation signal to generate an envelope signal by using the clock signal;
a first filter, arranged to filter out a first signal component in the envelope signal to generate a first filtered signal;
a second filter, arranged to filter out a second signal component in the envelope signal to generate a second filtered signal; and
a comparator, having a first input terminal for receiving the first filtered signal, a second input terminal for receiving the second filtered signal, and an output terminal for outputting the demodulation signal.
10. The signal demodulation apparatus of claim 9 , wherein a time constant of the first filter is substantially larger than the time constant of the second filter.
11. The signal demodulation apparatus of claim 9 , wherein the first filter is a low-pass filter arranged to filter out an AC (Alternating current) signal of the envelope signal, and to accordingly generate the first filtered signal.
12. The signal demodulation apparatus of claim 9 , wherein the second filter is a low-pass filter arranged to filter out a sampling noise of the envelope signal, and to accordingly generate the second filtered signal.
13. The signal demodulation apparatus of claim 9 , wherein the sample and hold circuit comprises:
a switch, having a first connecting terminal receiving the inputting modulation signal, a controlling terminal receiving the clock signal for selectively coupling the inputting modulation signal to a second connecting terminal of the switch; and
a capacitor, having a first terminal coupled the second connecting terminal of the switch, and a second terminal coupled to a reference voltage;
wherein the envelope signal is a signal on the first terminal of the capacitor.
14. The signal demodulation apparatus of claim 9 , wherein the first filter comprises:
a first resistor, having a first terminal receiving the envelope signal;
a first capacitor, having a first terminal coupled to a second terminal of the first resistor, and a second terminal coupled to a reference voltage;
a second resistor, having a first terminal coupled to the second terminal of the first resistor; and
a second capacitor, having a first terminal coupled to a second terminal of the second resistor, and a second terminal coupled to the reference voltage;
wherein the first filtered signal is a signal on the first terminal of the second capacitor.
15. The signal demodulation apparatus of claim 9 , wherein the second filter comprises:
a first resistor, having a first terminal receiving the envelope signal;
a first capacitor, having a first terminal coupled to a second terminal of the first resistor, and a second terminal coupled to a reference voltage;
a second resistor, having a first terminal coupled to the second terminal of the first resistor; and
a second capacitor, having a first terminal coupled to a second terminal of the second resistor, and a second terminal coupled to the reference voltage;
wherein the second filtered signal is a signal on the first terminal of the second capacitor.
16. A signal demodulation method, comprising:
generating a clock signal according to an inputting modulation signal; and
demodulating the inputting modulation signal to generate a demodulation signal according to the clock signal;
wherein a signal edge of the clock signal substantially aligns to a turning point of the inputting modulation signal;
wherein the step of generating the clock signal according to the inputting modulation signal comprises:
providing a comparator having a first input terminal for receiving the inputting modulation signal;
providing a first transistor having a first connecting terminal for receiving the inputting modulation signal, a second connecting terminal coupled to a second input terminal of the comparator, and a controlling terminal coupled to an output terminal of the comparator;
providing a second transistor having a controlling terminal coupled to the output terminal of the comparator, and a first connecting terminal coupled to a reference voltage;
providing a resistor having a first terminal coupled to a second connecting terminal of the second transistor, and a second terminal coupled to the second connecting terminal of the first transistor; and
providing a capacitor having a first terminal coupled to the second connecting terminal of the first transistor, and a second terminal coupled to the reference voltage;
wherein the clock signal is a signal on the output terminal of the comparator.
17. The signal demodulation method of claim 16 , wherein the turning point of the inputting modulation signal is a peak or a valley of the inputting modulation signal.
18. The signal demodulation method of claim 16 , wherein the step of demodulating the inputting modulation signal to generate the demodulation signal according to the clock signal comprises:
sampling the inputting modulation signal to generate an envelope signal by using the clock signal;
filtering out a first signal component in the envelope signal to generate a first filtered signal;
filtering out a second signal component in the envelope signal from the first filtered signal to generate a second filtered signal; and
comparing the second filtered signal and a first reference voltage to generate the demodulation signal.
19. The signal demodulation method of claim 18 , wherein the step of filtering out the first signal component in the envelope signal to generate the first filtered signal comprises:
changing a DC (Direct current) signal of the envelope signal into the first reference voltage to accordingly generate the first filtered signal.
20. The signal demodulation method of claim 18 , wherein the step of filtering out the second signal component in the envelope signal to generate the second filtered signal comprises:
filtering out a sampling noise of the envelope signal to accordingly generate the second filtered signal.
21. The signal demodulation method of claim 16 , wherein the step of demodulating the inputting modulation signal to generate the demodulation signal according to the clock signal comprises:
sampling the inputting modulation signal to generate an envelope signal by using the clock signal;
filtering out a first signal component in the envelope signal to generate a first filtered signal;
filtering out a second signal component in the envelope signal to generate a second filtered signal; and
comparing the first filtered signal and the second filtered signal to generate the demodulation signal.
22. The signal demodulation method of claim 21 , wherein the step of filtering out the first signal component in the envelope signal to generate the first filtered signal comprises:
filtering out an AC (Alternating current) signal of the envelope signal to accordingly generate the first filtered signal.
23. The signal demodulation method of claim 21 , wherein the step of filtering out the second signal component in the envelope signal to generate the second filtered signal comprises:
filtering out a sampling noise of the envelope signal to accordingly generate the second filtered signal.