IP Library Granted Patent US 9,523,995
Granted Patent B2
US 9,523,995 · App. 14/804,536 · Granted Dec 20, 2016

Reference voltage circuit

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Quick Facts
Patent No.
US 9,523,995
App. No.
14/804,536
Granted
Dec 20, 2016
Kind
B2
Abstract

Provided is a reference voltage circuit with improved temperature characteristics. A current based on a current flowing through a first depletion transistor whose gate and source are connected to each other is caused to flow through a third depletion transistor having the same threshold, to thereby generate a voltage between a gate and a source of the third depletion transistor. A current based on a current flowing through a second depletion transistor whose gate and source are connected to each other is caused to flow through a fourth depletion transistor having the same threshold, to thereby generate a voltage between a gate and a source of the fourth depletion transistor. A reference voltage is generated based on a difference voltage of the two voltages, to thereby obtain a reference voltage having less voltage fluctuations with respect to a temperature change.

Claims (12)

1. A reference voltage circuit, comprising:

a first constant voltage circuit and a second constant voltage circuit, wherein the first constant voltage circuit includes:

a first depletion transistor including a gate and a source which are connected to each other, and a drain connected to a first power supply terminal;

a first MOS transistor including a gate and a drain which are connected to the gate and the source of the first depletion transistor, and a source connected to a second power supply terminal;

a second MOS transistor including a gate connected to the gate of the first MOS transistor, a source connected to the second power supply terminal, and a drain connected to an output terminal of the first constant voltage circuit; and

a third depletion transistor including a gate connected to the second power supply terminal, a drain connected to the first power supply terminal, and a source connected to the drain of the second MOS transistor, wherein the second constant voltage circuit includes:

a second depletion transistor having a threshold different from a threshold of the first depletion transistor, including a gate and a source which are connected to each other, and a drain connected to the first power supply terminal;

a third MOS transistor including a gate and a drain which are connected to the gate and the source of the second depletion transistor, and a source connected to the second power supply terminal;

a fourth MOS transistor including a gate connected to the gate of the third MOS transistor, a source connected to the second power supply terminal, and a drain connected to an output terminal of the second constant voltage circuit; and

a fourth depletion transistor including a gate connected to the second power supply terminal, a drain connected to the first power supply terminal, and a source connected to the drain of the fourth MOS transistor, and

wherein the reference voltage circuit generates a reference voltage based on a potential difference between an output voltage of the first constant voltage circuit and an output voltage of the second constant voltage circuit.

2. The reference voltage circuit according to claim 1 , further comprising differential amplifier means, wherein the differential amplifier means receives the output voltage of the first constant voltage circuit and the output voltage of the second constant voltage circuit as inputs, and generates the reference voltage based on the potential difference between the output voltage of the first constant voltage circuit and the output voltage of the second constant voltage circuit.

Assignments (4)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 037783 FRAME: 0166. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 23, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 037903/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION .
Reel/Frame 037783/0166 →