Gate signal line drive circuit and display device
View Patent ↗A gate signal line driving circuit includes plural basic circuits, each outputting to a gate signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: agate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period to apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.
1. A display device comprising:
a plurality of pixels arranged in a matrix;
a plurality of gate signal lines each applying a gate signal to the corresponding pixels; and
a gate signal line driving circuit outputting the gate signals to the plurality of gate signal lines,
wherein the gate signal line driving circuit comprises:
a plurality of shift register basic circuits each of which outputs to the corresponding gate signal line the gate signal which has a high voltage during a high signal period and has a low voltage during a low signal period that is a period other than the high signal period,
wherein each of the shift register basic circuits comprises:
a first transistor which is in an ON state in accordance with the high signal period to apply the high voltage to the corresponding gate signal line;
a second transistor which is in an ON state in accordance with the low signal period to apply the low voltage to the corresponding gate signal line;
a third transistor which is turned on to apply the low voltage to the corresponding gate signal line in at least a part of a period until the second transistor is turned on after the first transistor is turned off;
a fourth transistor which applies an OFF voltage to a control electrode of the second transistor in an ON state; and
a fifth transistor which applies an OFF voltage to a control electrode of the fourth transistor,
wherein a common ON control signal is input to both the control electrode of the fourth transistor and a control electrode of the first transistor, and both the fourth transistor and the first transistor are turned on by the common ON control signal, and
wherein the control electrode of the second transistor is electrically connected to the control electrode of the fifth transistor of a subsequent stage of the shift register basic circuit.
2. The display device according to claim 1 , wherein the gate signal of the subsequent stage is input to a control electrode of the third transistor of each of the shift register basic circuits.
3. The display device according to claim 1 , wherein each of the shift register basic circuits further comprises a sixth transistor which has an output electrode electrically connected to the control electrode of the second transistor and a control electrode a first clock signal of two-phase clock signals with different phases being input to.
4. The display device according to claim 3 , wherein each of the shift register basic circuits further comprises a seventh transistor which applies a second clock signal of the two-phase clock signals to an input electrode of the sixth transistor.
5. The display device according to claim 4 , wherein a voltage of the input electrode of the sixth transistor is boosted by the first clock signal applied to the control electrode of the sixth transistor and is output to the control electrode of the second transistor.
6. The display device according to claim 4 , wherein each of the shift register basic circuits further comprises an eighth transistor which is electrically connected between the seventh transistor and the sixth transistor and has a control electrode electrically connected to an ON voltage.
7. A display device comprising:
a plurality of pixels arranged in a matrix;
a plurality of gate signal lines each applying a gate signal to the corresponding pixels;
a plurality of data signal lines each applying a data signal to the corresponding pixels; and
agate signal line driving circuit outputting the gate signals to the plurality of gate signal lines,
wherein the gate signal line driving circuit comprises:
a plurality of shift register basic circuits each of which outputs to the corresponding gate signal line the gate signal which has a high voltage during a high signal period of one screen display period and has a low voltage during a low signal period that is a period other than the high signal period,
wherein each of the shift register basic circuits comprises:
a first transistor which is in an ON state in accordance with the high signal period to apply the high voltage to the corresponding gate signal line;
a second transistor which is in an ON state in accordance with the low signal period to apply the low voltage to the corresponding gate signal line;
a third transistor which is turned on to apply the low voltage to the corresponding gate signal line in at least apart of a period until the second transistor is turned on after the first transistor is turned off;
a fourth transistor which applies an OFF voltage to a control electrode of the second transistor in an ON state; and
a fifth transistor which applies an OFF voltage to a control electrode of the fourth transistor,
wherein an output of a previous stage of the shift register basic circuit is input to both the control electrode of the fourth transistor and a control electrode of the first transistor, and both the fourth transistor and the first transistor are turned on by the output of the previous stage of the shift register basic circuit, and
wherein the control electrode of the second transistor is electrically connected to the control electrode of the fifth transistor of a subsequent stage of the shift register basic circuit.
8. The display device according to claim 7 , wherein the gate signal of the subsequent stage is input to a control electrode of the third transistor of each of the shift register basic circuits.
9. The display device according to claim 7 , wherein each of the shift register basic circuits further comprises a sixth transistor which has an output electrode electrically connected to the control electrode of the second transistor and a control electrode a first clock signal of two-phase clock signals with different phases being input to.
10. The display device according to claim 9 , wherein each of the shift register basic circuits further comprises a seventh transistor which applies a second clock signal of the two-phase clock signals to an input electrode of the sixth transistor.
11. The display device according to claim 10 , wherein a voltage of the input electrode of the sixth transistor is boosted by the first clock signal applied to the control electrode of the sixth transistor and is output to the control electrode of the second transistor.
12. The display device according to claim 10 , wherein each of the shift register basic circuits further comprises an eighth transistor which is electrically connected between the seventh transistor and the sixth transistor and has a control electrode electrically connected to an ON voltage.