THERMAL ENHANCEMENT FOR QUAD FLAT NO LEAD (QFN) PACKAGES
Integrated circuit packages with enhanced thermal characteristics are provided. For example, in embodiments, a QFN (quad flat no lead) package includes a die pad that extends to at least one pinless edge of the QFN package body. A portion of the die pad further extends towards a top surface of the QFN package body. By doing so, a low impedance thermal path from a die included in the QFN package to the top of the QFN package body is formed, which causes heat generated by the die to dissipate from one or more sides and the top of the QFN package, and ultimately to the surrounding environment. Furthermore, the path travelled by the heat in a circuit board coupled to the QFN package is shortened, thereby protecting electrical components coupled thereto.
1 . A quad flat no-lead (QFN) package, comprising:
a body having opposing first and second surfaces and a plurality of perimeter edges, the body comprising:
a die pad having one or more first surfaces and a second surface opposing the one or more first surfaces of the die pad, a first of the one or more first surfaces of the die pad configured to mount an integrated circuit die, the second surface of the die pad forming a portion of the second surface of the body, and
a plurality of pins peripherally positioned along a subset of the perimeter edges of the second surface of the body, at least one of the perimeter edges being pinless; and
the die pad extending to at least one pinless perimeter edge of the body.
2 . The QFN package of claim 1 , wherein a second of the one or more first surfaces of the die pad forms a first portion of the first surface of the body.
3 . The QFN package of claim 2 , wherein the second of the one or more first surfaces of the die pad is configured to mount a heat sink.
4 . The QFN package of claim 2 , further comprising:
an encapsulating material that encapsulates the integrated circuit die and the first of the one or more surfaces of the die pad, a surface portion of the encapsulating material forming a second portion of the first surface of the body.
5 . The QFN package of claim 4 , wherein the second of the one or more first surfaces of the die pad and the surface portion of the encapsulating material are coplanar.
6 . The QFN package of claim 1 , wherein the die pad is configured to be mounted to a printed circuit board.
7 . The QFN package of claim 1 , further comprising:
a plurality of bond wires coupled between a plurality of pads of the integrated circuit die and the plurality of pins.
8 . A method for assembling a quad flat no-lead (QFN) package comprising a body having opposing first and second surfaces, comprising:
forming a lead frame that comprises:
a plurality of pins peripherally positioned along a subset of perimeter edges of the lead frame, at least one of the perimeter edges being pinless; and
a die pad having one or more first surfaces and a second surface opposing the one or more first surfaces of the die pad, a first of the one or more first surfaces of the die pad configured to mount an integrated circuit die, the second surface of the die pad forming a portion of the second surface of the body, the die pad extending to at least one pinless perimeter edge of the lead frame; and
mounting the integrated circuit die to the die pad.
9 . The method of claim 8 , wherein a second of the one or more first surfaces of the die pad forms a first portion of the first surface of the body.
10 . The method of claim 9 , further comprising:
mounting a heat sink to at least the second of the one or more first surfaces of the die pad.
11 . The method of claim 9 , further comprising:
encapsulating the integrated circuit die and the first of the one or more first surfaces of the die pad with an encapsulating material, wherein a surface portion of the encapsulating material forms a second portion of the first surface of the body.
12 . The method of claim 11 , wherein the second of the one or more first surfaces of the die pad and the surface portion of the encapsulating material are coplanar.
13 . The method of claim 8 , further comprising:
attaching a plurality of bond wires between a plurality of pads of the integrated circuit die and the plurality of pins.
14 . A no-lead integrated circuit (IC) package, comprising:
a body having opposing first and second surfaces and four perimeter edges, the body comprising:
a die pad having one or more first surfaces and a second surface opposing the one or more first surfaces of the die pad, a first of the one or more first surfaces of the die pad configured to mount an IC die, the second surface of the die pad forming a portion of the second surface of the body, and
a plurality of pins peripherally positioned along three of the four perimeter edges of the second surface of the body, a fourth perimeter edge of the perimeter edges being pinless; and
the die pad extending to the fourth perimeter edge of the body.
15 . The no-lead IC package of claim 14 , wherein a second of the one or more first surfaces of the die pad forms a first portion of the first surface of the body.
16 . The no-lead IC package of claim 15 , wherein the second of the one or more first surfaces of the die pad is configured to mount a heat sink.
17 . The no-lead IC package of claim 15 , further comprising:
an encapsulating material that encapsulates the integrated circuit die and the first of the one or more surfaces of the die pad, a surface portion of the encapsulating material forming a second portion of the first surface of the body.
18 . The no-lead IC package of claim 17 , wherein the second of the one or more first surfaces of the die pad and the surface portion of the encapsulating material are coplanar.
19 . The no-lead IC package of claim 14 , wherein the die pad is configured to be mounted to a printed circuit board.
20 . The no-lead IC package of claim 14 , further comprising:
a plurality of bond wires coupled between a plurality of pads of the integrated circuit die and the plurality of pins.