Successive approximation analog-to-digital converter (ADC) with dynamic search algorithm
View Patent ↗Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.
1. A method of an analog-to-digital converter, comprising:
selecting, by the analog-to-digital converter, a reference voltage;
updating, by the analog-to-digital converter, the reference voltage based on an indication of how far an analog input voltage is from the reference voltage; and
repeating, one or more times by the analog-to-digital converter, said updating to obtain a digital output code representative of the analog input voltage.
2. The method of claim 1 , further comprising determining the indication of how far the analog input voltage is from the reference voltage based upon settling behavior of a comparator that is configured to compare the reference voltage to the analog input voltage.
3. The method of claim 1 , further comprising:
comparing, via a comparator of the analog-to-digital converter, the analog input voltage to the reference voltage;
determining that the analog input voltage is close to the reference voltage in response to the comparator having a first settling time during said comparing; and
determining that the analog input voltage is far from the reference voltage in response to the comparator having a second settling time during said comparing;
wherein the second settling time is shorter than the first settling time.
4. The method of claim 1 , further comprising:
comparing, via a comparator of the analog-to-digital converter, the analog input voltage to the reference voltage;
determining that the analog input voltage is close to the reference voltage in response to the comparator having a first voltage slope time during said comparing; and
determining that the analog input voltage is far from the reference voltage in response to the comparator having a second voltage slope during said comparing;
wherein the second voltage slope is greater than the first voltage slope.
5. The method of claim 1 , further comprising:
comparing, via a comparator of the analog-to-digital converter, the analog input voltage to the reference voltage;
determining that the analog input voltage is close to the reference voltage in response to the comparator having a first overshoot during said comparing; and
determining that the analog input voltage is far from the reference voltage in response to the comparator having a second overshoot during said comparing;
wherein the second overshoot is greater than the first overshoot.
6. The method of claim 1 , wherein said updating comprises selecting between a faster back-off process and a slower back-off process of the reference voltage based on the indication of how far the analog input voltage is from the reference voltage.
7. The method of claim 1 , wherein said updating comprises:
selecting a first back-off process that updates the reference voltage at a first rate in response to determining that the analog input voltage is a first distance from the reference voltage; and
selecting a second back-off process that updates the reference voltage at a second rate in response to determining that the analog input voltage is a second distance from the reference voltage;
wherein the first distance is less than the second distance; and
wherein the first rate is less than the second rate.
8. The method of claim 1 , further comprising outputting a flag signal that indicates whether the digital output code was obtained early with respect to a baseline number of comparisons.
9. The method of claim 1 , further comprising outputting a flag signal that indicates whether the digital output code was obtained late with respect to a baseline number of comparisons.
10. The method of claim 1 , wherein said selecting is based on peak-to-average power ratio of the analog input voltage.
11. A successive approximation analog-to-digital converter, comprising:
a digital-to-analog converter operable to generate a reference voltage based on a digital reference code;
a comparator operable to compare an analog input voltage to the reference voltage generated by the digital-to-analog converter and generate a comparison output indicative of the comparison; and
a search and decode logic module comprising one or more circuits operable to:
select the digital reference code;
update the digital reference code based on the comparison output and an indication of how far the analog input voltage is from the reference voltage; and
repeat, one or more times, said update of the digital reference code to obtain a digital output code representative of the analog input voltage.
12. The successive approximation analog-to-digital converter of claim 11 , wherein the one or more circuits of the search and decode logic module are further operable to determine the indication of how far the analog input voltage is from the reference voltage based upon settling behavior of the comparator.
13. The successive approximation analog-to-digital converter of claim 11 , wherein the one or more circuits of the search and decode logic module are further operable to:
determine that the analog input voltage is close to the reference voltage in response to the comparator having a first settling time; and
determine that the analog input voltage is far from the reference voltage in response to the comparator having a second settling time;
wherein the second settling time is shorter than the first settling time.
14. The successive approximation analog-to-digital converter of claim 11 , wherein the one or more circuits of the search and decode logic module are further operable to:
determine that the analog input voltage is close to the reference voltage in response to the comparator having a first voltage slope time; and
determine that the analog input voltage is far from the reference voltage in response to the comparator having a second voltage slope;
wherein the second voltage slope is greater than the first voltage slope.
15. The successive approximation analog-to-digital converter of claim 11 , wherein the one or more circuits of the search and decode logic module are further operable to:
determine that the analog input voltage is close to the reference voltage in response to the comparator having a first overshoot; and
determine that the analog input voltage is far from the reference voltage in response to the comparator having a second overshoot;
wherein the second overshoot is greater than the first overshoot.
16. The successive approximation analog-to-digital converter of claim 11 , wherein the one or more circuits of the search and decode logic module are further operable to select between a faster back-off process and a slower back-off process of the reference voltage based on the indication of how far the analog input voltage is from the reference voltage.
17. The successive approximation analog-to-digital converter of claim 11 , wherein the one or more circuits of the search and decode logic module are further operable to:
select a first back-off process that updates the reference voltage at a first rate in response to determining that the analog input voltage is a first distance from the reference voltage; and
select a second back-off process that updates the reference voltage at a second rate in response to determining that the analog input voltage is a second distance from the reference voltage;
wherein the first distance is less than the second distance; and
wherein the first rate is less than the second rate.
18. The successive approximation analog-to-digital converter of claim 11 , wherein the one or more circuits of the search and decode logic module are further operable to output a flag signal that indicates whether the digital output code was obtained early with respect to a baseline number of comparisons.
19. The successive approximation analog-to-digital converter of claim 11 , wherein the one or more circuits of the search and decode logic module are further operable to output a flag signal that indicates whether the digital output code was obtained late with respect to a baseline number of comparisons.
20. The successive approximation analog-to-digital converter of claim 11 , wherein the one or more circuits of the search and decode logic module are further operable to select the digital reference code based on peak-to-average power ratio of the analog input voltage.