Electro-mechanical oscillator and method for generating a signal
View Patent ↗An oscillator and method for generating a signal are provided. The oscillator comprises an electro-mechanical resonator and a reconfigurable oscillator driver. The reconfigurable oscillator driver starts the oscillator in single-ended mode to avoid latching and transitions the oscillator to differential mode in such a manner as to sustain oscillations therein. The reconfigurable oscillator driver comprises two back-to-back banks of inverters and an adjustable feedback resistor. In single-ended mode, one bank is disabled and the other bank is enabled. To transition to differential mode and improve the quality of the signal, the number of enabled inverters is equalized in both banks.
1. An oscillator, comprising:
a resonator input configured to receive, from an electro-mechanical resonator, a resonator signal for creating oscillations in the oscillator;
two back-to-back banks of inverters coupled by a direct current (DC) connection to the resonator input, each of the banks comprising two or more inverters, the inverters programmable to contribute a gain to the oscillations in the oscillator; and
a controller in communication with the banks of inverters, the controller configured to program each of the banks to contribute a different gain to the oscillations in the oscillator when starting oscillations to inhibit the oscillator from latching to a non-oscillatory direct current stable state.
2. The oscillator of claim 1 , wherein the controller is configured to enable a different number of inverters in each of the banks of inverters to program each of the banks of inverters to contribute the different gain.
3. The oscillator of claim 1 , wherein the controller is further configured to reduce the difference between the gain contributed by each of the banks of inverters to improve the phase noise of the oscillations.
4. The oscillator of claim 3 , wherein the controller is further configured to reduce an overall gain contributed by the inverters, in association with reducing the difference between the gain contributed by each of the banks of inverters, to inhibit latching to a non-oscillatory direct current stable state.
5. The oscillator of claim 3 , wherein the controller is configured to enable or disable one of the inverters in one of the banks of inverters to reduce the difference between the gain contributed by each of the banks of inverters.
6. The oscillator of claim 3 , wherein the controller is configured to equalize the gain contributed by each of the banks of inverters.
7. The oscillator of claim 3 , wherein the controller is configured to equalize the number of inverters enabled in each of the banks of inverters.
8. The oscillator of claim 3 , wherein the controller is configured to, in response to the oscillations reaching a steady amplitude state after reducing the difference between the gain contributed by each of the banks of inverters, increase the gain contributed by the inverters to increase the amplitude or improve the phase noise of the oscillations.
9. The oscillator of claim 4 , further comprising an adjustable negative feedback resistor connected in parallel with the banks of back-to-back inverters and in communication with the controller, the controller configured to decrease the resistance of the adjustable negative feedback resistor to reduce the overall gain contributed by the inverters.
10. The oscillator of claim 1 , further comprising an electro-mechanical resonator connected to the resonator input, the electro-mechanical resonator comprising a bulk acoustic wave resonator, a thin-film bulk acoustic resonator, a surface acoustic wave resonator, or a quartz crystal resonator, integrated with the oscillator in either one of a System-in-Package (SiP) and System-on-Chip (SoC) device.
11. A method for generating oscillations, comprising:
receiving a signal from an electro-mechanical resonator;
programming two back-to-back banks of two or more inverters to contribute a different gain to the signal to generate the oscillations and inhibit latching to a non-oscillatory direct current stable state; and
in response to the oscillations reaching a steady amplitude state, reducing the difference between the gain contributed by each of the banks of inverters to improve the phase noise of the oscillations.
12. The method of claim 11 , wherein programming the inverters comprises enabling a different number of inverters in each of the banks of inverters.
13. The method of claim 11 , further comprising reducing an overall gain contributed by the inverters, in association with reducing the difference between the gain contributed by each of the banks of inverters, to inhibit latching to a non-oscillatory direct current stable state.
14. The method of claim 11 , wherein reducing the difference between the gain contributed by each of the banks of inverters comprises enabling or disabling one of the inverters in one of the banks of inverters.
15. The method of claim 11 , wherein, reducing the difference between the gain contributed by each of the banks of inverters comprises equalizing the gain contributed by each of the banks of inverters.
16. The method of claim 11 , wherein, reducing the difference between the gain contributed by each of the banks of inverters comprises equalizing the number of inverters enabled in each of the banks of inverters.
17. The method of claim 11 , further comprising, in response to the oscillations reaching a steady amplitude state after reducing the difference between the gain contributed by each of the banks of inverters, increasing the overall gain contributed by the inverters to increase the amplitude or improve the phase noise of the oscillations.
18. The method of claim 12 , wherein the inverters are enabled or disabled one at a time, and further comprising permitting oscillations to reach a steady amplitude state between enabling or disabling each of the inverters.
19. The method of claim 13 , wherein decreasing the overall gain contributed by the inverters comprises decreasing a resistance of a negative feedback resistor connected in parallel with each of the banks of inverters.
20. The method of claim 17 , wherein increasing the overall gain contributed by the inverters comprises increasing a resistance of a negative feedback resistor connected in parallel with each of the banks of inverters.