METHOD, SYSTEM, AND APPARATUS FOR MEMORY WITH FEEDTHROUGH AND RETIMING PATHS TO SUPPORT MEMORY TO MEMORY REQUESTS
Memory systems, such as SRAM systems, are described that comprise a series of adjacently placed memory components for providing memory data and memory transaction information from one component to another. Input pins are strategically placed, and muxing and ancillary logic are included within memory components, to allow for the adjacent placement. The memory data and memory transaction information are provided by a memory component in a configurable feedthrough or pipelined manner based on the period of an operating clock. The memory data and memory transaction information are received by a memory system at only a first memory component in the series, and are provided from the memory system by only a last memory component in the series. Memory components selectively provide to subsequent memory components in the series either locally stored data, or data received by the memory components as an input.
1 . A memory system that comprises:
a first memory component that includes within, a first selection component and a first retiming register; and
a second memory component that includes within, a second selection component;
the first memory component being configured to:
receive memory transaction information that is input to the memory system, and read data, and
provide to the second memory component the memory transaction information and, based on the first selection component, selectively provide first read data stored in the first memory component as a first buffered output, or as a first registered output from the first retiming register; and
the second memory component being configured to:
receive the memory transaction information and the first read data from the first memory component, and
provide the memory transaction information, and provide the first read data or second read data stored in the second memory component as an output of the second memory component based on the second selection component.
2 . The memory system of claim 1 , wherein the memory system comprises a series of memory components and wherein the first memory component is configured to receive the memory transaction information and the read data from a previous memory component in the series of memory components, the read data being previous read data stored in the previous memory component.
3 . The memory system of claim 1 , wherein the memory system comprises a series of memory components and wherein the second memory component is configured to provide the output to a subsequent memory component in the series of memory components.
4 . The memory system of claim 1 , wherein the first memory component is configured to receive the memory transaction information from a source external to the memory system, and is the only memory component of the memory system to receive the memory transaction information from the source.
5 . The memory system of claim 1 , wherein the second memory component is configured to provide at least a portion of the output to a receiver external to the memory system, and is the only memory component of the memory system to provide a respective output to the receiver.
6 . The memory system of claim 1 , wherein the first memory component and the second memory component are SRAM components.
7 . The memory system of claim 1 , wherein the first memory component and the second memory component are adjacent to each other at a respective component edge with no physical, external connections therebetween.
8 . The memory system of claim 1 , wherein the second memory component includes within, a second retiming register;
the second memory component configured to:
provide the first read data or the second read data as a second buffered output, or as a second registered output from the second retiming register.
9 . The memory system of claim 8 , wherein the second memory component includes within, a third selection component;
the third selection component configured to determine whether the first read data or the second read data is provided as the second buffered output or as the second registered output.
10 . A memory system that comprises:
a first memory component that includes within, a first retiming register; and
a second memory component that includes within, a second retiming register;
the first memory component configured to:
receive memory transaction information input to the memory system, wherein the memory transaction information comprises one or more of write request information, write data or read request information, and
selectively provide to the second memory component the memory transaction information as a first buffered output, or as a first registered output from the first retiming register; and
the second memory component configured to:
receive the memory transaction information from the first memory component, and
selectively provide the memory transaction information as a second buffered output, or as a second registered output from the second retiming register.
11 . The memory system of claim 10 , wherein the first memory component includes within, a first selection component, and wherein the second memory component includes within, a second selection component;
the first selection component configured to determine whether the memory transaction information is provided as the first buffered output or as the first registered output; and
the second selection component configured to determine whether the memory transaction information is provided as the second buffered output or as the second registered output.
12 . The memory system of claim 10 , wherein the first registered output and the second registered output are respectively selected based at least on a clock frequency of the memory system.
13 . The memory system of claim 10 , wherein at least one of the first retiming register or the second retiming register is further configured as an input register for at least a portion of the memory transaction information to the first memory component and the second memory component, respectively.
14 . The memory system of claim 10 , wherein the read request information comprises at least one of:
bank identification information; or
a read address.
15 . The memory system of claim 10 , wherein the first memory component is configured to receive the memory transaction information:
from a previous memory component in a series of memory components that comprise the memory system; or
from a source external to the memory system, wherein the first memory component is the only memory component of the memory system to receive the memory transaction information from the source.
16 . The memory system of claim 10 , wherein the second memory component is configured to provide the output:
to a subsequent memory component in a series of memory components that comprise the memory system; or
to a receiver external to the memory system, wherein the second memory component is the only memory component of the memory system to provide a respective output to the receiver.
17 . A method performed in a memory system, the method comprising:
receiving memory transaction information input to the memory system at a first memory component of the memory system;
selectively providing the memory transaction information from the first memory component to a second memory component of the system as a first buffered output or as a first registered output;
receiving the memory transaction information at the second memory component from the first memory component; and
selectively providing the memory transaction information from the second memory component as a second buffered output or as a second registered output.
18 . The method of claim 17 , further comprising:
receiving memory data stored in the first memory component by the second memory component, the memory data being read from the first memory component according a read operation associated with the memory transaction information; and
providing the memory data by the second memory component as an output of the second memory component.
19 . The method of claim 18 , further comprising:
selectively providing the memory data from the first memory component to the second memory component as a third buffered output or as a third registered output.
20 . The method of claim 17 , wherein the memory transaction information comprises write data and a write request to the second memory component;
the method further comprising storing the write data at the second memory component.