Apparatus and method for phase locked loop bandwidth expansion
View Patent ↗An apparatus for PLL bandwidth expansion including a compensation filter and a phase locked loop, where the compensation filter is programmed with a compensation function derived based on programmable coefficients and parameters of a transmitting device, a frequency response of the phase locked loop, and a wanted frequency response.
1. An apparatus for phase locked loop (“PLL”) bandwidth expansion comprising:
a transmitting device including a programmable hardware compensation filter configured to receive a transmitted signal and output a filtered signal, and a PLL circuit installed in front of the compensation filter and configured to receive the filtered signal and output a modulated carrier signal, the programmable hardware compensation filter configured to be programmed with a compensation function having filter coefficients,
wherein the filter coefficients are determined from programmable coefficients and parameters stored on the transmitting device, and
wherein a function of the programmable hardware compensation filter (“Fcomp(s)”) is:
Fcomp
(
s
)
=
y
0
·
(
s
5
+
s
4
·
x
4
+
s
3
·
x
3
+
s
2
·
x
2
+
s
·
x
1
+
x
0
)
x
1
·
(
s
5
+
s
4
·
z
4
+
s
3
·
z
3
+
s
2
·
z
2
+
s
·
z
1
+
z
0
)
,
where
x
0
=
a
·
K
ϕ
A
·
b
·
w
n
2
·
K
vco
N
x
1
=
K
ϕ
A
·
b
·
w
n
2
·
K
vco
N
x
2
=
w
n
2
·
b
,
x
3
=
w
n
2
+
2
ξ
·
w
n
·
b
x
4
=
w
n
2
+
2
ξ
·
w
n
·
b
y
0
=
wa
4
y
1
=
b
1
·
wa
3
y
2
=
b
2
·
wa
2
y
3
=
b
3
·
wa
z
0
=
y
0
·
x
0
x
1
z
1
=
y
0
+
y
1
·
x
0
x
1
z
2
=
y
1
+
y
2
·
x
0
x
1
z
3
=
y
2
+
y
3
·
x
0
x
1
z
4
=
y
3
+
x
0
x
1
and where s is a Laplace transform operator (jw), x 0 , x 1 , x 2 , x 3 , x 4 , y 0 , y 1 , y 2 , y 3 , z 0 , z 1 , z 2 , z 3 , and z 4 , are the filter coefficients, and K φ , K vco , A, N, a, b, w n , wa, and ξ are the programmable coefficients and parameters such that K φ includes phase detector gain, K vco includes voltage controlled oscillator gain, A includes a gain value, N includes a variable divider value, a includes a ‘zero’, b includes a ‘pole’, w n includes a filter natural frequency, wa is a desired bandwidth, and ξ includes a damping factor, and
wherein a frequency response of the PLL circuit combined with the programmable hardware compensation filter (“Freq(s)”) is:
Freq
(
s
)
=
wa
4
s
4
+
s
3
·
b
3
·
wa
+
s
2
·
b
2
·
wa
2
+
s
·
b
1
·
wa
3
+
wa
4
.
2. The apparatus of claim 1 , wherein a transfer function of the PLL circuit is:
PLL
(
s
)
=
s
·
x
1
+
x
0
s
5
+
s
4
·
x
4
+
s
3
·
x
3
+
s
2
·
x
2
+
s
·
x
1
+
x
0
.
3. The apparatus of claim 2 , wherein the compensation function is based on the transfer function of the PLL circuit and a wanted frequency response.
4. The apparatus of claim 1 , wherein the transmitting device is a Very Small Aperture Terminal that includes an indoor unit and an outdoor unit.
5. The apparatus of claim 4 , wherein the PLL circuit is included within one of the indoor unit and the outdoor unit.
6. The apparatus of claim 4 , wherein the programmable hardware compensation filter is included within the indoor unit and the programmable coefficients are included within the outdoor unit.
7. The apparatus of claim 4 , wherein indoor unit includes a processor configured to:
read the programmable coefficients within the outdoor unit responsive to the outdoor unit being connected to the indoor unit;
determine the compensation function based on the read programmable coefficients; and
implement the compensation function within the programmable hardware compensation filter.
8. The apparatus of claim 1 , wherein the transmitting device includes:
at least one of a phase modulator and a frequency modulator located between the PLL circuit; and
the programmable hardware compensation filter, and
wherein the transmitting device is configured to i) modulate a filtered signal from the programmable hardware compensation filter using a reference clock to produce a modulated reference signal, and ii) transmit the modulated reference signal to the PLL circuit.
9. The apparatus of claim 1 , wherein K φ =2/(2π), K vco =2π*375e 6 , A =0.53, N=32, a =2π*37.7e 3 , b =2π*9.9e 6 , w n =2π*15.65e 6 , and ξ=0.462.
10. The apparatus of claim 1 , wherein b 1 =2.6, b 2 =3.4, and b 3 =2.6.
11. The apparatus of claim 1 , wherein a transfer function of the PLL circuit is:
PLL
(
s
)
=
s
·
x
1
+
x
0
s
5
+
s
4
·
x
4
+
s
3
·
x
3
+
s
2
·
x
2
+
s
·
x
1
+
x
0
.
12. An apparatus for phase locked loop (“PLL”) bandwidth expansion comprising:
a programmable hardware compensation filter configured to receive an input signal and output a filtered signal; and
a PLL circuit installed in front of the programmable hardware compensation filter and configured to receive the filtered signal and output a modulated carrier signal,
wherein the programmable hardware compensation filter is programmed with a compensation function having filter coefficients that are determined from programmable coefficients and parameters of a transmitting device, a frequency response of the PLL circuit, and a wanted frequency response, and
wherein the compensation function (“Fcomp(s)”) is:
Fcomp
(
s
)
=
y
0
·
(
s
5
+
s
4
·
x
4
+
s
3
·
x
3
+
s
2
·
x
2
+
s
·
x
1
+
x
0
)
x
1
·
(
s
5
+
s
4
·
z
4
+
s
3
·
z
3
+
s
2
·
z
2
+
s
·
z
1
+
z
0
)
,
where
x
0
=
a
·
K
ϕ
A
·
b
·
w
n
2
·
K
vco
N
x
1
=
K
ϕ
A
·
b
·
w
n
2
·
K
vco
N
x
2
=
w
n
2
·
b
,
x
3
=
w
n
2
+
2
ξ
·
w
n
·
b
x
4
=
w
n
2
+
2
ξ
·
w
n
·
b
y
0
=
wa
4
y
1
=
b
1
·
wa
3
y
2
=
b
2
·
wa
2
y
3
=
b
3
·
wa
z
0
=
y
0
·
x
0
x
1
z
1
=
y
0
+
y
1
·
x
0
x
1
z
2
=
y
1
+
y
2
·
x
0
x
1
z
3
=
y
2
+
y
3
·
x
0
x
1
z
4
=
y
3
+
x
0
x
1
and where s is a Laplace transform operator (jw), x 0 , x 1 , x 2 , x 3 , x 4 , y 0 , y 1 , y 2 , y 3 , z 0 , z 1 , z 2 , z 3 , and z 4 , are the filter coefficients, and K φ , K vco , A, N, a, b, w n , wa, and ξ are the programmable coefficients and parameters such that K φ includes phase detector gain, K vco includes voltage controlled oscillator gain, A includes a gain value, N includes a variable divider value, a includes a ‘zero’, b includes a ‘pole’, w n includes a filter natural frequency, wa is a desired bandwidth, and ξ includes a damping factor, and
wherein a frequency response of the PLL combined with the programmable hardware compensation filter (“Freq(s)”) is:
Freq
(
s
)
=
wa
4
s
4
+
s
3
·
b
3
·
wa
+
s
2
·
b
2
·
wa
2
+
s
·
b
1
·
wa
3
+
wa
4
.
13. The apparatus of claim 12 , wherein the compensation function is a function for the wanted frequency response divided by a function for the frequency response of the PLL circuit.
14. The apparatus of claim 12 , wherein the programmable hardware compensation filter and the PLL circuit in combination produce a Butterworth response.
15. The apparatus of claim 12 , wherein the programmable hardware compensation filter includes at least one of an application specific integrated circuit, a field programmable gate array, and a combination of an application specific integrated circuit and a filed programmable gate array.
16. The apparatus of claim 12 , wherein the transmitting device includes a Very Small Aperture Terminal and at least a portion of the programmable coefficients and parameters are stored in an outdoor unit of the Very Small Aperture Terminal.
17. A method for phase locked loop (“PLL”) bandwidth expansion comprising:
reading, via a processor, programmable coefficients and parameters stored within an outdoor unit of a transmitting device;
determining, via the processor, a compensation function including filtering coefficients based on the programmable coefficients and parameters, the compensation function relating to a function for a frequency response of a PLL circuit configured to receive a filtered signal and output a modulated carrier signal, which is installed in front of a programmable hardware compensation filter configured to receive an input signal and output the filtered signal that includes the compensation function; and
implementing, via the processor, the compensation function of the programmable hardware compensation filter within the transmitting device,
wherein the compensation function (“Fcomp(s)”) is:
Fcomp
(
s
)
=
y
0
·
(
s
5
+
s
4
·
x
4
+
s
3
·
x
3
+
s
2
·
x
2
+
s
·
x
1
+
x
0
)
x
1
·
(
s
5
+
s
4
·
z
4
+
s
3
·
z
3
+
s
2
·
z
2
+
s
·
z
1
+
z
0
)
,
where
x
0
=
a
·
K
ϕ
A
·
b
·
w
n
2
·
K
vco
N
x
1
=
K
ϕ
A
·
b
·
w
n
2
·
K
vco
N
x
2
=
w
n
2
·
b
,
x
3
=
w
n
2
+
2
ξ
·
w
n
·
b
x
4
=
w
n
2
+
2
ξ
·
w
n
·
b
y
0
=
wa
4
y
1
=
b
1
·
wa
3
y
2
=
b
2
·
wa
2
y
3
=
b
3
·
wa
z
0
=
y
0
·
x
0
x
1
z
1
=
y
0
+
y
1
·
x
0
x
1
z
2
=
y
1
+
y
2
·
x
0
x
1
z
3
=
y
2
+
y
3
·
x
0
x
1
z
4
=
y
3
+
x
0
x
1
and where s is a Laplace transform operator (jw), x 0 , x 1 , x 2 , x 3 , x 4 , y 0 , y 1 , y 2 , y 3 , z 0 , z 1 , z 2 , z 3 , and z 4 , are the filter coefficients, and K φ , K vco , A, N, a, b, w n , wa, and ξ are the programmable coefficients and parameters such that K φ includes phase detector gain, K vco includes voltage controlled oscillator gain, A includes a gain value, N includes a variable divider value, a includes a ‘zero’, b includes a ‘pole’, w n includes a filter natural frequency, wa is a desired bandwidth, and ξ includes a damping factor, and
wherein a frequency response of the PLL circuit combined with the programmable hardware compensation filter (“Freq(s)”) is:
Freq
(
s
)
=
wa
4
s
4
+
s
3
·
b
3
·
wa
+
s
2
·
b
2
·
wa
2
+
s
·
b
1
·
wa
3
+
wa
4
.
18. The method of claim 17 , further comprising:
determining the outdoor unit has been communicatively coupled to an indoor unit of the transmitting device; and
responsive to determining the outdoor unit has been communicatively coupled to the indoor unit, reading the programmable coefficients and parameters.
19. The method of claim 18 , wherein the indoor unit includes a set-top-box receiver and the outdoor unit includes a satellite dish, and wherein the outdoor unit is communicatively coupled to the indoor unit during a television or Internet installation procedure.
20. The method of claim 17 , wherein a transfer function of the PLL circuit is:
PLL
(
s
)
=
s
·
x
1
+
x
0
s
5
+
s
4
·
x
4
+
s
3
·
x
3
+
s
2
·
x
2
+
s
·
x
1
+
x
0
.
21. The method of claim 20 , wherein the compensation function is related to a function for a wanted frequency response divided by the transfer function of the PLL circuit.
22. The method of claim 17 , further comprising communicating with a satellite after implementing the compensation function within the transmitting device.