Sense amplifier and semiconductor device for securing operation margin of sense amplifier

1. A sense amplifier comprising:

an equalization unit configured to precharge a pair of bit lines to a level of a bit line precharge voltage in response to a bit line equalizing signal;

an amplification unit configured to sense and amplify voltages of the pair of bit lines, supply, during an active operation, a ground voltage to a pull-down node of a latch section, and supply, a first voltage lower than the ground voltage to the pull-down node of the latch section during a period from a point of time when a precharge signal is enabled to before the bit line equalizing signal is enabled; and

a driving signal control circuit configured to disable the bit line equalizing signal and enable a word line when an active signal is enabled, enable a first driving signal after a predetermined delay time when the active signal is enabled, and disable the first driving signal and enable a second driving signal when the precharge signal is enabled,

wherein the driving signal control circuit comprises:

a bank control block configured to generate an inverted signal of the bit line equalizing signal, a pull-up driving signal, a first pull-down driving signal and a second pull-down driving signal in response to the active signal and the precharge signal; and

a sense amplifier driving block configured to drive the inverted signal of the bit line equalizing signal, the pull-up driving signal, the first pull-down driving signal and the second pull-down driving signal, and output the bit line precharge signal, the first driving signal and the second driving signal,

wherein the bank control block comprises:

a command control unit configured to output the active signal and the precharge signal in response to a bank control signal;

a first delay unit configured to delay the active signal;

a second delay unit configured to delay the precharge signal;

a driving signal generation unit configured to generate the inverted signal of the bit line equalizing signal in response to the active signal and an output of the second delay unit;

a pull-up control unit configured to generate the pull-up driving signal in response to the output of the second delay unit and an output of the first delay unit;

a first pull-down control unit configured to drive the output of the first delay unit and the precharge signal; and

a second pull-down control unit configured to control the first pull-down driving signal and the second pull-down driving signal in response to the output of the second delay unit and an output of the first pull-down control unit.

2. The sense amplifier according to claim 1 , wherein the first voltage is a minus voltage.

3. The sense amplifier according to claim 1 , wherein the amplification unit comprises:

a latch section configured to sense and amplify the voltages of the pair of bit lines;

a first pull-down section configured to supply the ground voltage to the latch section in response to a first driving signal;

a second pull-down section configured to supply the first voltage to the latch section in response to a second driving signal; and

a pull-up section configured to selectively supply a core voltage to the latch section in response to a third driving signal.

4. The sense amplifier according to claim 3 , wherein the first pull-down section comprises a first NMOS transistor coupled between the pull-down node of the latch section and a terminal to which the ground voltage is applied, and wherein the NMOS transistor is driven by the first driving signal.

5. The sense amplifier according to claim 3 , wherein the second pull-down section comprises a second NMOS transistor coupled between the pull-down node of the latch section and a terminal to which the first voltage is applied, and wherein the second NMOS transistor is driven by the second driving signal.

6. The sense amplifier according to claim 3 , wherein the pull-up section comprises a PMOS transistor coupled between the latch section and a terminal to which the core voltage is applied, and wherein the PMOS transistor is driven by the third driving signal.

7. The sense amplifier according to claim 3 , wherein, when an active signal is enabled in the active operation, the pull-up section is enabled after a predetermined delay time has passed.

8. The sense amplifier according to claim 3 , wherein, when an active signal is enabled in the active operation, the first pull-down section is enabled after the predetermined delay time has passed.

9. The sense amplifier according to claim 3 , wherein, when the precharge signal is enabled, the first pull-down section is disabled and the second pull-down section is enabled.

10. The sense amplifier according to claim 3 , wherein the second pull-down section retains an enabled state during a period from a point of time when the precharge signal is enabled to before the bit line equalizing signal is enabled.

11. The sense amplifier according to claim 3 , wherein the pull-up section retains an enabled state during a period in which the first pull-down section and the second pull-down section operate.

12. The sense amplifier according to claim 1 , wherein the sense amplifier driving block is formed in a repeater region.

13. A semiconductor device comprising:

a sense amplifier configured to precharge a pair of bit lines to a level of a bit line precharge voltage in response to a bit line equalizing signal, and sense and amplify data of the pair of bit lines in response to driving voltages applied to a pull-up power line and a pull-down power line; and

a sense amplifier control circuit configured to supply a core voltage to the pull-up power line in response to a pull-up driving signal, and supply a minus voltage lower than a ground voltage to the pull-down power line in response to a pull-down driving signal during a period from a point of time when a precharge signal is enabled to before the bit line equalizing signal is enabled,

wherein the sense amplifier control circuit comprises:

a driving signal generation unit configured to generate the pull-up driving signal and the pull-down driving signal in response to an active signal and the precharge signal; and

a sense amplifier driving block configured to supply the core voltage to the pull-up power line in response to the pull-up driving signal, and supply the minus voltage to the pull-down power line in response to the pull-down driving signal,

wherein, after a predetermined delay time from when an active signal is enabled, the pull-up driving signal and a driving signal are enabled, and the ground voltage is supplied to the pull-down power line for a predetermined time, and

wherein, when the precharge signal is enabled, the driving signal is disabled and the pull-down driving signal is enabled, and the minus voltage is supplied to the pull-down power line until the bit line equalizing signal is enabled.

14. The semiconductor device according to claim 13 , wherein the sense amplifier comprises:

an equalization unit configured to precharge the pair of bit lines to the level of the bit line precharge voltage in response to the bit line equalizing signal;

an amplification unit configured to sense and amplify voltages of the pair of bit lines in response to the driving voltages applied to the pull-up power line and the pull-down power line; and

a pull-down unit configured to supply the ground voltage to the pull-down power line in response to the driving signal in an active operation.

15. The semiconductor device according to claim 13 , wherein the sense amplifier driving block comprises:

a pull-up driving unit configured to supply the core voltage to the pull-up power line in response to the pull-up driving signal;

a precharge unit configured to precharge the pull-up power line and the pull-down power line in response to the bit line equalizing signal; and

a pull-down driving unit configured to supply the minus voltage to the pull-down power line in response to the pull-down driving signal.