Noise shaped interpolator and decimator apparatus and method
View Patent ↗An interpolator or decimator includes an elastic storage element in the signal path between first and second clock domains. The elastic element may, for example, be a FIFO which advantageously allows short term variation in sample clocks to be absorbed. A feedback mechanism controls a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.
1. A method for interpolation or decimation, comprising:
generating an error signal related to a difference between a first clock signal for a first clock domain and a second clock signal of a second clock domain;
filtering the error signal;
delta-sigma modulating the filtered error signal;
generating a clock period signal based at least in part on the modulated filtered signal; and
in response to the clock period signal, enabling an elastic storage element disposed between the first and second clock domains to asynchronously output data from or input data to the elastic storage element.
2. The method of claim 1 , wherein generating the clock period signal comprises modulo counting the modulated filtered signal.
3. The method of claim 1 , wherein said difference between the first clock signal and the second clock signal is a rate of change in a number of entries of said data in the elastic storage element.
4. The method of claim 1 , wherein the difference between the first clock signal and a second clock signal comprises an integral of a difference between a rate of first clock signal and a rate of the second clock signal.
5. An interpolation or decimation circuit, comprising:
an elastic storage element disposed between a first clock signal for a first clock domain and a second clock signal of a second clock domain;
a differencing circuit configured to generate an error signal related to a difference between the first and second clock signals;
a filter circuit configured to filter the error signal;
a delta-sigma modulator circuit configured to modulate the filtered error signal; and
a counter circuit configured to generate a clock period signal based at least in part on the modulated filtered signal;
wherein the elastic storage element includes an enable input that receives the clock period signal to control asynchronously outputting data from or inputting data to the elastic storage element.
6. The circuit of claim 5 , wherein the counter circuit comprises a modulo counter responsive to the modulated filtered signal.
7. The circuit of claim 5 , wherein said difference between the first clock signal and the second clock signal is a rate of change in a number of entries of said data in the elastic storage element.
8. The circuit of claim 5 , wherein the difference between the first clock signal and a second clock signal comprises an integral of a difference between a rate of first clock signal and a rate of the second clock signal.
9. A method, comprising:
clocking data into an elastic buffer in accordance with a first clock signal;
generating an error signal related to a difference between the first clock signal and a second clock signal;
filtering the error signal;
delta-sigma modulating the filtered error signal;
generating a clock period signal based at least in part on the modulated filtered signal; and
reading data from the elastic buffer in response to the clock period signal.
10. The method of claim 9 , wherein generating the clock period signal is responsive to said second clock signal.
11. The method of claim 10 , wherein generating the clock period signal comprises modulo counting the modulated filtered signal.
12. The method of claim 9 , wherein modulating the filtered error signal is responsive to the clock period signal.
13. The method of claim 9 , further comprising applying a user selected offset in generating the error signal.
14. The method of claim 9 , wherein said difference between the first clock signal and the second clock signal is a rate of change in a number of entries of said data in the elastic buffer.
15. The method of claim 9 , wherein the difference between the first clock signal and a second clock signal comprises an integral of a difference between a rate of first clock signal and a rate of the second clock signal.
16. A method, comprising:
clocking data out of an elastic buffer in accordance with a first clock signal;
generating an error signal related to a difference between the first clock signal and a second clock signal;
filtering the error signal;
delta-sigma modulating the filtered error signal;
generating a clock period signal based at least in part on the modulated filtered signal; and
writing data into the elastic buffer in response to the clock period signal.
17. The method of claim 16 , wherein generating the clock period signal is responsive to said first clock signal.
18. The method of claim 17 , wherein generating the clock period signal comprises modulo counting the modulated filtered signal.
19. The method of claim 16 , wherein modulating the filtered error signal is responsive to the clock period signal.
20. The method of claim 16 , further comprising applying a user selected offset in generating the error signal.
21. The method of claim 16 , wherein said difference between the first clock signal and the second clock signal is a rate of change in a number of entries of said data in the elastic buffer.
22. The method of claim 16 , wherein the difference between the first clock signal and the second clock signal comprises an integral of a difference between a rate of first clock signal and a rate of the second clock signal.