Packet processing on a multi-core processor
View Patent ↗A method for packet processing on a multi-core processor. According to one embodiment of the invention, a first set of one or more processing cores are configured to include the capability to process packets belonging to a first set of one or more packet types, and a second set of one or more processing cores are configured to include the capability to process packets belonging to a second set of one or more packet types, where the second set of packet types is a subset of the first set of packet types. Packets belonging to the first set of packet types are processed at a processing core of either the first or second set of processing cores. Packets belonging to the second set of packet types are processed at a processing core of the first set of processing cores.
1. A method for packet processing on a multiprocessor system, the method comprising:
receiving a first packet;
receiving a second packet;
identifying that the first packet belongs to a first flow of packets of a plurality of flows of packets;
identifying that the second packet belongs to a second flow of packets of the plurality of flows of packets;
assigning the first packet to be processed at a first set of one or more processors of the multiprocessor system; and
assigning the second packet to be processed at a second set of one or more processors of the multiprocessor system, wherein:
the first packet is processed at the first set of one or more processors,
the second packet is locked by a processor at the second set of one or more processors,
at least a portion of the second packet is processed before the second packet is locked,
the processed portion of the second packet is associated with a processing phase of the second packet, and
the processing of the second packet continues after the second packet has been unlocked.
2. The method of claim 1 , further comprising identifying that the lock on the second packet has been unlocked, wherein the processing of the second packet continues at the second set of one or more processors after the lock on the second packet is unlocked.
3. The method of claim 1 , further comprising:
receiving an initial packet prior to receiving the second packet;
identifying that the initial packet belongs to the second flow of packets; and
assigning the initial packet to be processed at the second set of processors, wherein at least a portion of the initial packet is processed at the second set of one or more processors, and the processing of the at least portion of the initial packet locks the second packet.
4. The method of claim 1 , wherein the first packet flow or the second packet flow is associated with at least one of a source Internet Protocol (IP) address, a particular source port, a particular destination port, and a particular protocol.
5. The method of claim 1 , further comprising storing the second packet after the second packet has been locked and until the second packet is unlocked.
6. The method of claim 5 , wherein:
the second packet is stored in a de-schedule queue; and
the second packet is sent to the second set of one or more processors for the continued processing after the second packet is unlocked.
7. A non-transitory computer readable storage medium having embodied thereon a program executable by a processor to perform a method for packet processing on a multiprocessor system, the method comprising:
receiving a first packet;
receiving a second packet;
identifying that the first packet belongs to a first flow of packets of a plurality of flows of packets;
identifying that the second packet belongs to a second flow of packets of the plurality of flows of packets;
assigning the first packet to be processed at a first set of one or more processors of the multiprocessor system; and
assigning the second packet to be processed at a second set of one or more processors of the multiprocessor system, wherein:
the first packet is processed at the first set of one or more processors, and
the second packet is locked by a processor at the second set of one or more processors, wherein:
at least a portion of the second packet is processed before the second packet is locked;
the processed portion of the second packet is associated with a processing phase of the second packet, and
the processing of the second packet continues after the second packet has been unlocked.
8. The non-transitory computer readable storage medium of claim 7 , the program further executable to identify that the lock on the second packet has been unlocked, wherein the processing of the second packet continues at the second set of one or more processors after the lock on the second packet is unlocked.
9. The non-transitory computer readable storage medium of claim 7 , the processor is further executable to:
receive an initial packet prior to receiving the second packet;
identify that the initial packet belongs to the second flow of packets; and
assign the initial packet to be processed at the second set of processors, wherein at least a portion of the initial packet is processed at the second set of one or more processors, and the processing of the at least portion of the initial packet locks the second packet.
10. The non-transitory computer readable storage medium of claim 7 , wherein the first packet flow or the second packet flow is associated with at least one of a source Internet Protocol (IP) address, a particular source port, a particular destination port, and a particular protocol.
11. The non-transitory computer readable storage medium of claim 7 , the program further executable to store the second packet after the second packet has been locked and until the second packet is unlocked.
12. The non-transitory computer readable storage medium of claim 11 , wherein:
the second packet is stored in a de-schedule queue; and
the packet is sent to the second set of one or more processors for the continued processing after the second packet is unlocked.
13. An apparatus that performs a method for packet processing, the apparatus comprising:
a network interface, wherein a first packet and a second packet are received over the network interface;
a memory; and
a processor executing instructions out of the memory, wherein the processor is coupled to a first set and a second set of one or more processors, and the processor:
identifies that the first packet belongs to a first flow of packets of a plurality of flows of packets;
identifies that the second packet belongs to a second flow of packets of the plurality of flows of packets;
assigns the first packet to be processed at the first set of one or more processors of the multiprocessor system; and
assigns the second packet to be processed at the second set of one or more processors, wherein:
the first packet is processed at the first set of one or more processors,
the second packet is locked by a processor at the second set of one or more processors,
at least a portion of the second packet is processed before the second packet is locked,
the processed portion of the second packet is associated with a processing phase of the second packet, and
the processing of the second packet continues after the second packet has been unlocked.
14. The apparatus of claim 13 , wherein the processor identifies that the lock on the second packet has been unlocked and the processing of the second packet continues at the second set of one or more processors after the lock on the second packet is unlocked.
15. The apparatus of claim 13 , wherein the network interface receives an initial packet prior to receiving the second packet, and the processor:
identifies that the initial packet belongs to the second flow of packets, and
assigns the initial packet to be processed at the second set of processors, wherein at least a portion of the initial packet is processed at the second set of one or more processors, and the processing of the at least portion of the initial packet locks the second packet.
16. The apparatus of claim 13 , wherein the first packet flow or the second packet flow is associated with at least one of a source Internet Protocol (IP) address, a particular source port, a particular destination port, and a particular protocol.
17. The apparatus of claim 13 , wherein the second packet is stored in the memory after the second packet is locked and until the second packet is unlocked.