Electrostatic discharge (ESD) protection circuit
View Patent ↗An electrostatic discharge (ESD) protection circuit is disclosed. In this regard, an ESD protection circuit is provided to protect an integrated circuit (IC) from an ESD event. In one aspect, an ESD voltage detection circuitry activates an ESD clamping circuitry when an ESD voltage associated with faster voltage rise time is detected between a supply rail and a ground rail. In another aspect, an operation voltage detection circuitry deactivates the ESD clamping circuitry when an operation voltage associated with slower voltage rise time is detected between the supply rail and the ground rail. By differentiating the ESD voltage from the operation voltage based on respective voltage rise times, it is possible to prevent the ESD clamping circuitry from missing the ESD voltage associated with the faster voltage rise time or being falsely activated by the operation voltage associated with the slower voltage rise time.
1. An electrostatic discharge (ESD) protection circuit in an integrated circuit (IC) comprising:
an ESD clamping circuitry coupled between a supply rail and a ground rail and configured to discharge an ESD event in an IC;
first voltage detection circuitry coupled between the supply rail and the ground rail and configured to generate a first detection signal when an ESD voltage having a first rise time is detected between the supply rail and the ground rail;
second voltage detection circuitry coupled between the supply rail and the ground rail and configured to generate a second detection signal when an operation voltage, which has a second rise time that is greater than fifty times the first rise time, is detected between the supply rail and the ground rail; and
latch circuitry coupled to the first voltage detection circuitry and the second voltage detection circuitry, the latch circuitry configured to:
activate the ESD clamping circuitry to discharge the ESD event in response to the first detection signal independent of the second detection signal; and
deactivate the ESD clamping circuitry in response to the second detection signal.
2. The ESD protection circuit of claim 1 wherein the first voltage detection circuitry is further configured to generate the first detection signal as logical zero in response to detecting the ESD voltage and wherein the first rise time is greater than or equal to two nanoseconds (2 ns) and less than or equal to fifteen nanoseconds (15 ns).
3. The ESD protection circuit of claim 1 wherein the first voltage detection circuitry is further configured to generate the first detection signal as logical zero in response to detecting the ESD voltage and wherein the first rise time is greater than or equal to five nanoseconds (5 ns) and less than or equal to ten nanoseconds (10 ns).
4. The ESD protection circuit of claim 1 wherein the second voltage detection circuitry is further configured to generate the second detection signal as logical one in response to detecting the operation voltage and wherein the second rise time is greater than or equal to one half of a microsecond (0.5 μs) and less than or equal to four microseconds (4 μs).
5. The ESD protection circuit of claim 1 wherein the second voltage detection circuitry is further configured to generate the second detection signal as logical one in response to detecting the operation voltage and wherein the second rise time is greater than or equal to one millisecond (1 ms) and less than or equal to one and a half milliseconds (1.5 ms).
6. The ESD protection circuit of claim 1 wherein the first voltage detection circuitry comprises:
a resistor and a capacitor disposed in a serial arrangement;
the resistor having a resistance of approximately ten kiloohms (10 KΩ); and
the capacitor having a capacitance of approximately five hundred femtofarad (500 fF) and configured to be fully charged between two nanosecond (2 ns) and fifteen nanoseconds (15 ns).
7. The ESD protection circuit of claim 1 wherein the second voltage detection circuitry comprises:
a p-type metal-oxide semiconductor (pMOS) resistor and a capacitor disposed in a serial arrangement;
the pMOS resistor having a variable resistance; and
the capacitor having a capacitance of approximately one picofarad (1 pF) and configured to be fully charged between one half of a microsecond (0.5 μs) and four microseconds (4 μs).
8. The ESD protection circuit of claim 1 wherein the ESD clamping circuitry further comprises a device selected from the group consisting of: an n-type metal-oxide semiconductor (nMOS) array; a p-type metal-oxide semiconductor (pMOS) array; a bipolar device; and a Darlington pair.
9. The ESD protection circuit of claim 1 wherein the latch circuitry comprises a cross-coupled negative-and (NAND) logic comprising:
a reset terminal (R terminal) coupled to the first voltage detection circuitry to receive the first detection signal as an R signal;
a set terminal (S terminal) coupled to the second voltage detection circuitry via an inverter, the inverter configured to invert the second detection signal and provide the inverted second detection signal to the S terminal as an S signal; and
an output terminal ( Q terminal) coupled to the ESD clamping circuitry via an inversion logic, the inversion logic configured to convert a Q signal outputted by the Q terminal into a control signal to activate or deactivate the ESD clamping circuitry.
10. The ESD protection circuit of claim 9 wherein the inversion logic comprises an even number of inverters disposed in a serial arrangement.
11. The ESD protection circuit of claim 10 wherein the latch circuitry is further configured to:
generate the Q signal as logical one to activate the ESD clamping circuitry in response to receiving the R signal as logical zero and the S signal as logical one; and
generate the Q signal as logical zero to deactivate the ESD clamping circuitry in response to receiving the R signal as logical one and the S signal as logical zero.
12. The ESD protection circuit of claim 1 wherein the latch circuitry comprises a cross-coupled negative-and (NAND) logic comprising:
a reset terminal (R terminal) coupled to the first voltage detection circuitry to receive the first detection signal as an R signal;
a set terminal (S terminal) coupled to the second voltage detection circuitry via an inverter, the inverter configured to invert the second detection signal and provide the inverted second detection signal to the S terminal as an S signal; and
an output terminal (Q terminal) coupled to the ESD clamping circuitry via an inversion logic, the inversion logic configured to convert a Q signal outputted by the Q terminal into a control signal to activate or deactivate the ESD clamping circuitry.
13. The ESD protection circuit of claim 12 wherein the inversion logic comprises an odd number of inverters disposed in a serial arrangement.
14. The ESD protection circuit of claim 13 wherein the latch circuitry is further configured to:
generate the Q signal as logical one to activate the ESD clamping circuitry in response to receiving the R signal as logical zero and the S signal as logical one; and
generate the Q signal as logical zero to deactivate the ESD clamping circuitry in response to receiving the R signal as logical one and the S signal as logical zero.
15. The ESD protection circuit of claim 1 wherein the latch circuitry comprises a cross-coupled negative-or (NOR) logic comprising:
a set terminal (S terminal) coupled to the first voltage detection circuitry via an inverter, the inverter configured to invert the first detection signal and provide the inverted first detection signal to the S terminal as an S signal;
a reset terminal (R terminal) coupled to the second voltage detection circuitry to receive the second detection signal as an R signal; and
an output terminal ( Q terminal) coupled to the ESD clamping circuitry via an inversion logic, the inversion logic configured to convert a Q signal outputted by the Q terminal into a control signal to activate or deactivate the ESD clamping circuitry.
16. The ESD protection circuit of claim 15 wherein the inversion logic comprises an odd number of inverters disposed in a serial arrangement.
17. The ESD protection circuit of claim 16 wherein the latch circuitry is further configured to:
generate the Q signal as logical zero to activate the ESD clamping circuitry in response to receiving the S signal as logical one and the R signal as logical zero; and
generate the Q signal as logical one to deactivate the ESD clamping circuitry in response to receiving the S signal as logical zero and the R signal as logical one.
18. The ESD protection circuit of claim 1 wherein the latch circuitry comprises a cross-coupled negative-or (NOR) logic comprising:
a set terminal (S terminal) coupled to the first voltage detection circuitry via an inverter, the inverter configured to invert the first detection signal and provide the inverted first detection signal to the S terminal as an S signal;
a reset terminal (R terminal) coupled to the second voltage detection circuitry to receive the second detection signal as an R signal; and
an output terminal (Q terminal) coupled to the ESD clamping circuitry via an inversion logic, the inversion logic configured to convert a Q signal outputted by the Q terminal into a control signal to activate or deactivate the ESD clamping circuitry.
19. The ESD protection circuit of claim 18 wherein the inversion logic comprises an even number of inverters disposed in a serial arrangement.
20. The ESD protection circuit of claim 19 wherein the latch circuitry is further configured to:
generate the Q signal as logical one to activate the ESD clamping circuitry in response to receiving the S signal as logical one and the R signal as logical zero; and
generate the Q signal as logical zero to deactivate the ESD clamping circuitry in response to receiving the S signal as logical zero and the R signal as logical one.