IP Library Granted Patent US 9,337,172
Granted Patent B2
US 9,337,172 · App. 14/822,253 · Granted May 10, 2016

Semiconductor device

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Quick Facts
Patent No.
US 9,337,172
App. No.
14/822,253
Granted
May 10, 2016
Kind
B2
Abstract

Provided is a small and thin semiconductor device while preventing contamination of a wire bonding terminal caused by creeping-up of a die bond. The semiconductor device includes: a first semiconductor chip having a main surface formed with electrodes; an extension part extended outward from a side end surface of the first semiconductor chip; a rewiring layer formed from the main surface of the first semiconductor chip to a first surface of the extension part; a connection terminal provided on the rewiring layer of the extension part; a die bond that fixes the first semiconductor chip and the extension part to a substrate; and in the extension part, a step outside the connection terminal.

Claims (50)

1. A semiconductor device comprising:

a first semiconductor chip having a main surface on which electrodes are formed;

an extension part extended outward from a side end surface of the first semiconductor chip;

a rewiring layer formed from the main surface of the first semiconductor chip to a first surface of the extension part;

a connection terminal provided on the rewiring layer of the extension part;

a die bond disposed between a rear surface of the first semiconductor chip and a substrate, and between a rear surface of the extension part and the substrate, so that the die bond fixes the first semiconductor chip and the extension part to the substrate; and

a step disposed outwardly from the connection terminal of the extension part in a direction away from the first semiconductor chip.

2. The semiconductor device according to claim 1 , wherein a second semiconductor chip is mounted on the main surface of the first semiconductor chip.

3. The semiconductor device according to claim 1 , wherein the connection terminal is a wire bonding terminal, and

the connection terminal is connected with an electrode pad by a wire, the electrode pad being provided on a surface of the substrate on which the first semiconductor chip is mounted.

4. A semiconductor device comprising:

a first semiconductor chip having a main surface on which electrodes are formed;

an extension part extended outward from a side end surface of the first semiconductor chip;

a rewiring layer formed from the main surface of the first semiconductor chip to a first surface of the extension part;

a connection terminal provided on the rewiring layer of the extension part;

a die bond that fixes the first semiconductor chip and the extension part to a substrate; and

a step disposed outside the connection terminal of the extension part,

wherein the step is a first step formed by the first surface of the extension part and an end of the rewiring layer formed inside an end of the extension part.

5. The semiconductor device according to claim 4 , wherein the rewiring layer has an insulation layer and a rewiring, and

the end of the rewiring layer that forms the first step is formed only of the insulation layer.

6. The semiconductor device according to claim 4 , wherein the rewiring layer has an insulation layer and a rewiring, and

the rewiring is exposed from the insulation layer at the end of the rewiring layer that forms the first step.

7. The semiconductor device according to claim 6 , wherein the die bond is a conductive paste, and

the die bond is in contact with the rewiring at the end of the rewiring layer that forms the first step.

8. The semiconductor device according to claim 4 wherein the step includes a second step formed stepwise by protruding a part of the end of the extension part.

9. The semiconductor device according to claim 8 , wherein the second step is formed by protruding a rear surface side of the extension part, and

a plurality of steps is formed by combining the second step with the first step.

10. The semiconductor device according to claim 8 , wherein the second step is formed by protruding a first surface side of the extension part, and

a plurality of steps is formed by combining the second step with the first step.

11. A semiconductor device comprising:

a first semiconductor chip having a main surface on which electrodes are formed;

an extension part extended outward from a side end surface of the first semiconductor chip;

a rewiring layer formed from the main surface of the first semiconductor chip to a first surface of the extension part;

a connection terminal provided on the rewiring layer of the extension part,

a die bond that fixes the first semiconductor chip and the extension part to a substrate; and

a step disposed outside the connection terminal of the extension part,

wherein the die bond covers at least a part of a side surface and the first surface of the extension part while avoiding an upper surface of the rewiring layer.

12. A semiconductor device comprising:

a first semiconductor chip having a main surface on which electrodes are formed;

an extension part extended outward from a side end surface of the first semiconductor chip;

a rewiring layer formed from the main surface of the first semiconductor chip to a first surface of the extension part;

a connection terminal provided on the rewiring layer of the extension part;

a die bond that fixes the first semiconductor chip and the extension part to a substrate; and

a step disposed outside the connection terminal of the extension part,

wherein the step is a second step formed stepwise by protruding a part of an end of the extension part.

13. The semiconductor device according to claim 12 , wherein the second step is formed by protruding a first surface side of the extension part.

14. The semiconductor device according to claim 13 , wherein the die bond covers at least a part of a side surface of the extension part and the second step while avoiding an upper surface of the rewiring layer.

15. The semiconductor device according to claim 12 , wherein the second step is formed by protruding a rear surface side of the extension part.

16. The semiconductor device according to claim 15 , wherein the die bond covers at least the second step while avoiding an upper surface and a side surface of the rewiring layer.

17. The semiconductor device according to claim 12 , wherein a side surface of the second step is tapered.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2015
From: DOHI, SHIGEFUMI
To: PANASONIC CORPORATION
Reel/Frame 036431/0461 →