IP Library Granted Patent US 9,601,461
Granted Patent B2
US 9,601,461 · App. 14/825,110 · Granted Mar 21, 2017

Semiconductor device and method of forming inverted pyramid cavity semiconductor package

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Quick Facts
Patent No.
US 9,601,461
App. No.
14/825,110
Granted
Mar 21, 2017
Kind
B2
Abstract

A semiconductor device has a first substrate. A conductive layer is formed over the first substrate. A first cavity is formed through the first substrate and extending to the conductive layer. A first semiconductor die including a plurality of first interconnect structures is disposed in the first cavity. A second substrate is disposed over the first substrate. A second cavity is formed through second substrate. A second semiconductor die including a plurality of second interconnect structures is disposed in the second cavity. A discrete device or third semiconductor die is disposed over the second semiconductor die. A plurality of third interconnect structures is formed between the second substrate and discrete device or third semiconductor die. The first, second, and third interconnect structures are reflowed simultaneously. An encapsulant is deposited over and around the first semiconductor die, the second semiconductor die, and the discrete device or third semiconductor die.

Claims (48)

1. A method of making a semiconductor device, comprising:

providing a first substrate;

forming an interconnect structure over the substrate;

forming a first cavity in the first substrate over the interconnect structure;

disposing a first semiconductor die in the first cavity on the interconnect structure;

providing a second substrate;

forming a second cavity through the second substrate;

disposing the second substrate over the first substrate;

disposing a second semiconductor die in the second cavity over the first cavity and extending outside a footprint of the first cavity; and

depositing an encapsulant over the first semiconductor die and second semiconductor die.

2. The method of claim 1 , further including disposing a discrete device over the second substrate.

3. The method of claim 1 , further including disposing a third semiconductor die over the second substrate.

4. The method of claim 3 , further including disposing a heat spreader over the third semiconductor die.

5. The method of claim 1 , further including:

forming a plurality of first conductive bumps over the first semiconductor die;

forming a plurality of second conductive bumps over the second semiconductor die; and

reflowing the first conductive bumps and second conductive bumps simultaneously with the first conductive bumps extending from the first semiconductor die to the interconnect structure and the second conductive bumps extending from the second semiconductor die to the first substrate.

6. The method of claim 1 , further including forming a conductive via through the first semiconductor die.

7. A method of making a semiconductor device, comprising:

providing a first substrate including a first conductive via;

forming a conductive layer over a first surface of the first substrate and coupled to the first conductive via;

forming a first cavity through the first substrate to expose the conductive layer;

disposing a first semiconductor die in the first cavity;

providing a second substrate including a second conductive via formed through the second substrate;

forming a second cavity through the second substrate with the second cavity including a width larger than a width of the first cavity;

disposing the second substrate over the first substrate with the first cavity aligned over the second cavity and the first conductive via coupled to the second conductive via and the conductive layer; and

disposing a second semiconductor die in the second cavity and on the first substrate.

8. The method of claim 7 , further including disposing a discrete device over the second semiconductor die and coupled to the first semiconductor die through the conductive layer, first conductive via, and second conductive via.

9. The method of claim 7 , further including disposing a third semiconductor die over the second semiconductor die and coupled to the first semiconductor die through the conductive layer, first conductive via, and second conductive via.

10. The method of claim 9 , further including disposing an encapsulant over the first semiconductor die, second semiconductor die, and third semiconductor die.

11. The method of claim 7 , further including depositing an encapsulant in the first cavity and second cavity.

12. The method of claim 7 , wherein the second cavity extends to a second surface of the first substrate.

13. The method of claim 7 , further including:

forming a plurality of first interconnect structures over the first semiconductor die;

forming a plurality of second interconnect structures over the second semiconductor; and

reflowing the first interconnect structures and second interconnect structures simultaneously.

14. A method of making a semiconductor device, comprising:

providing a first substrate;

forming a conductive layer over a surface of the first substrate;

forming a first cavity completely through the first substrate to expose the conductive layer through the first cavity;

disposing a first semiconductor die in the first cavity and electrically coupled to the conductive layer;

disposing a second substrate including a second cavity over the first substrate with the second cavity larger than the first cavity; and

disposing a second semiconductor die in the second cavity.

15. The method of claim 14 , wherein a portion of the first substrate is exposed within the second cavity.

16. The method of claim 15 , further including disposing the second semiconductor die over the portion of the first substrate exposed within the second cavity.

17. The method of claim 14 , further including disposing a passive device over the second substrate and second semiconductor die.

18. The method of claim 17 , further including depositing an encapsulant in the first cavity, in the second cavity, and over the passive device.

19. The method of claim 14 , further including disposing a heat spreader over the second semiconductor die.

Assignments (4)
ASSIGNMENT OF PATENT SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (040646/0799) Recorded Feb 17, 2023
From: HSBC BANK USA, NATIONAL ASSOCIATION, AS RESIGNING AGENT
To: JPMORGAN CHASE BANK, N.A., AS SUCCESSOR AGENT
Reel/Frame 062781/0544 →
SECURITY INTEREST Recorded Nov 17, 2016
From: SEMTECH CORPORATION; SEMTECH NEW YORK CORPORATION; SIERRA MONOLITHICS, INC.; SEMTECH EV, INC.; TRIUNE SYSTEMS, L.L.C.; TRIUNE IP, LLC
To: HSBC BANK USA, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 040646/0799 →
SECURITY INTEREST Recorded Dec 14, 2015
From: SEMTECH CORPORATION
To: HSBC BANK USA, NATIONAL ASSOCIATION
Reel/Frame 037284/0745 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 12, 2015
From: HO, KOK KHOON; CHINNUSAMY, SATYAMOORTHI
To: SEMTECH CORPORATION
Reel/Frame 036313/0492 →