Processor directly storing address range of co-processor memory accesses in a transactional memory where co-processor supplements functions of the processor
View Patent ↗Monitoring, by a processor having a cache, addresses accessed by a co-processor associated with the processor during transactional execution of a transaction by the processor. The processor executes a transactional memory (TM) transaction, including receiving, by the processor, a memory address range of data that a co-processor may access to perform a co-processor operation. The processor saves the memory address range. Based on receiving, by the processor, a cache coherency request that conflicts with the saved address range, the processor aborts the TM transaction.
1. A method for monitoring, by a processor having a cache, addresses in a main memory accessed directly by a co-processor associated with the processor during transactional execution of a transaction by the processor, the method comprising:
executing, by the processor, a transactional memory (TM) transaction, the executing comprising:
executing a co-processor address range-setting instruction, wherein the co-processor address range setting instruction includes a parameter for a user-specified main memory address range that is not in a read-set of the TM transaction, the co-processor address range-setting instruction execution comprising:
obtaining, in the user-specified parameter of the co-processor address range-setting instruction, the main memory address range of data that the co-processor may access;
and storing, directly by the processor, the main memory address range of data in one or more hardware registers;
and receiving, by the processor, a cache coherency request;
in response to determining, by the processor, that the cache coherency request does not conflict with an address range in the read-set of the TM transaction, and that the cache coherency request conflicts with the stored main memory address range, aborting the TM transaction.
2. A method in accordance with claim 1 :
wherein storing the main memory address range further comprises including an indicator indicating that the stored main memory address range is an active address range;
wherein receiving the cache coherency request that conflicts further comprises receiving a cache coherency request that conflicts with an address in the stored main memory address range that is indicated as being an active address range;
and wherein aborting the TM transaction further comprises changing the indicator to indicate that the stored main memory address range is not an active address range.
3. A method in accordance with claim 1 , wherein the one or more hardware registers are contained in a cache subsystem of a cache.
4. A method in accordance with claim 1 , wherein receiving a conflicting cache coherency request comprises receiving a conflicting cache coherency request on a multi-processor bus.
5. A method in accordance with claim 1 , wherein a conflicting cache coherency request is a request indicating an intent to store data to an address in the memory address range stored in the one or more hardware registers.