Semiconductor memory device which stores plural data in a cell
A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.
1. A semiconductor memory device comprising:
a memory cell capable of storing first bit-data and second bit-data;
a data storage circuit coupled to the memory cell via a bit line, and including a first cache and a second cache; and
a controller configured to control an operation of the data storage circuit,
wherein the first cache stores data transferred from an external,
the second cache stores data transferred from the first cache,
the controller inverts a logic level of the data stored in the second cache, and
the controller writes data to the memory cell when the inverted data stored in the second cache is a first logic level, and does not write data to the memory cell when the inverted data stored in the second cache is a second logic level.
2. The device according to claim 1 , wherein
the data storage circuit includes a third cache,
the third cache stores data transferred from the second cache, and
the second cache stores data read from the memory cell.
3. The device according to claim 2 , wherein
the controller inverts a logic level of the data stored in the first cache, and transfers the inverted data of the first cache to the third cache,
the controller inverts a logic level of the data stored in the second cache, and transfers the inverted data of the second cache to the first cache, and
the controller executes an AND operation on the data stored in the first cache and the third cache, and transfers the result of the AND operation to the second cache.
4. The device according to claim 3 , the controller writes data to the memory cell when the data stored in the second cache is the first logic level, and does not write data to the memory cell when the data stored in the second cache is the second logic level in a write operation of the second bit-data.
5. The device according to claim 1 , wherein the data storage circuit is coupled to the external.
6. The device according to claim 1 , wherein the data storage circuit receives data from the external when a write command is issued.
7. The device according to claim 1 , wherein the controller inverts the data in the data storage circuit while a program voltage is rising.
8. The device according to claim 1 , wherein the memory cell is a NAND cell.
9. The device according to claim 1 , further comprising a memory string including memory cells which are connected in serial,
wherein the memory string is connected to the bit line.