IP Library Granted Patent US 10,224,351
Granted Patent B2
US 10,224,351 · App. 14/826,744 · Granted Mar 5, 2019

Switchable solar cell devices

Inventor: Stephen Joseph Gaul (Melbourne Village, FL)
Assignee: INTERSIL AMERICAS LLC
H01L27/1421H01L29/7804H01L31/02H01L31/02008H01L31/02021H01L31/0504H01L31/112H01L31/18H02S10/00H02S40/34H02S40/36H02S50/00H02S50/10Y02E10/50
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Quick Facts
Patent No.
US 10,224,351
App. No.
14/826,744
Granted
Mar 5, 2019
Kind
B2
Abstract

Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.

Claims (14)

1. A method of operation of a solar cell element, comprising:

monitoring an electrical output of a solar cell area in the solar cell element, wherein the solar cell element comprising a p-type semiconductor terminal and an n-type semiconductor terminal;

determining if the electrical output is less than a predetermined value; and

bypassing the solar cell area in the solar cell element if the electrical output is less than the predetermined value, wherein the bypassing comprises controlling a source region or a drain region of a semiconductor switch, wherein the drain region is an n-type semiconductor region formed within a p-type semiconductor substrate of the solar cell element; wherein the n-type semiconductor terminal of the solar cell element being formed within the drain region of the semiconductor switch.

2. The method of claim 1 , wherein the bypassing comprises bypassing the electrical output of the solar cell area in the solar cell element.

3. The method of claim 1 , wherein the monitoring comprises reading the electrical output of the solar cell area in the solar cell element.

4. The method of claim 1 , wherein the monitoring comprises reading an electrical signal output across the p-type semiconductor terminal and the n-type semiconductor terminal of the solar cell element.

5. A method of operation of a solar cell element, comprising:

monitoring an electrical signal output from a solar cell area in a solar cell element, wherein the solar cell element including a p-n junction, a p-type semiconductor terminal and an n-type semiconductor terminal;

determining if the electrical signal output from the solar cell area is less than a value; and

controlling a switch component integrated together with the solar cell element to bypass the solar cell area if the electrical signal output from the solar cell area is less than the value, wherein the switch component comprises a source region and a drain region integrated together with the solar cell element, wherein the drain region is an n-type doped region of the p-n junction of the solar cell element, wherein the drain region is formed within a p-doped region of the p-n junction, and the n-type semiconductor terminal of the solar cell element is formed within the drain region of the switch component.

6. The method of claim 5 , wherein the monitoring comprises measuring the electrical signal output across the p-type semiconductor terminal and the n-type semiconductor terminal of the solar cell element.

7. The method of claim 5 , wherein the controlling comprises controlling the source region or the drain region of the switch component, wherein the switch component is a laterally diffused metal oxide semiconductor (LDMOS) transistor or a vertically diffused metal oxide semiconductor (VDMOS) transistor.

8. The method of claim 5 , wherein the solar cell element further comprises an external contact for connecting the solar cell element with an external circuitry.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF ASSIGNOR IN THE ASSIGNMENT DOCUMENT PREVIOUSLY RECORDED AT REEL: 036330 FRAME: 0719. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 10, 2015
From: GAUL, STEPHEN JOSEPH
To: INTERSIL AMERICAS INC.
Reel/Frame 036640/0545 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2015
From: GAUL, STEPHEN JOSEPH
To: INTERSIL AMERICAS INC.
Reel/Frame 036330/0719 →
CHANGE OF NAME Recorded Aug 14, 2015
From: INTERSIL AMERICAS INC.
To: INTERSIL AMERICAS LLC
Reel/Frame 036355/0867 →
Continuity (4)
Division 14023079 · Sep 10, 2013
Division 12470325 · May 21, 2009
Provisional Application 61147888 · Jan 28, 2009
Related Publication 20150357971A1 · Dec 10, 2015