Manufacturing method of a semiconductor device and method for creating a layout thereof
A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.
1. A semiconductor device comprising:
two adjacent functioning wirings including a first functioning wiring and a second functioning wiring;
a first electrically isolated torus-like conductor pattern area between the two adjacent functioning wirings; and
a first insulating film;
wherein the first electrically isolated torus-like conductor pattern area surrounds the first insulating film.
2. The semiconductor device according to claim 1 , wherein a third functioning wiring and a fourth functioning wiring are arranged at each outer side of the two adjacent functioning wirings, the third functioning wiring being spaced by a second insulating film from the outer side, the fourth functioning wiring being spaced by a third insulating film from the outer side.
3. The semiconductor device according to claim 2 , wherein an inner side of the first electrically isolated torus-like conductor pattern area is in contact with the first insulating film.
4. The semiconductor device according to claim 3 , comprising:
a second electrically isolated torus-like conductor pattern area between the two adjacent functioning wirings; and
a fourth insulating film;
wherein the second electrically isolated torus-like conductor pattern area surrounds the fourth insulating film.
5. The semiconductor device according to claim 4 , wherein the first electrically isolated torus-like conductor pattern area and the second electrically isolated torus-like conductor pattern area share a portion of each other.
6. The semiconductor device according to claim 5 , wherein each of the two adjacent functioning wirings is formed by using a double patterning method.
7. The semiconductor device according to claim 5 , wherein the two adjacent functioning wirings are arranged parallel.
8. The semiconductor device according to claim 7 , wherein the semiconductor device is a memory device and a part of each of the two adjacent functioning wirings is a bit line of the semiconductor device.
9. The semiconductor device according to claim 7 , wherein the semiconductor device is a memory device and a part of each of the two adjacent functioning wirings is a word line of the semiconductor device.
10. The semiconductor device according to claim 5 , wherein the first insulating film, the second insulating film, the third insulating film and the fourth insulating film are connected to an insulation layer below the two adjacent functioning wirings, the first electrically isolated torus-like conductor pattern area and the second electrically isolated torus-like conductor pattern area.
11. The semiconductor device according to claim 5 , wherein an inner side of the second electrically isolated torus-like conductor pattern area is in contact with the fourth insulating film.
12. The semiconductor device according to claim 5 , further comprising a second electrically isolated conductor pattern,
wherein the fourth insulating film includes a torus-like area which fully surrounds the second electrically isolated conductor pattern.
13. The semiconductor device according to claim 5 , further comprising:
a third electrically isolated torus-like conductor pattern area; and
a fifth insulating film;
wherein the third electrically isolated torus-like conductor pattern area surrounds the fifth insulating film, and
wherein the first electrically isolated torus-like conductor pattern area and the third electrically isolated torus-like conductor pattern area share a portion of each other.
14. The semiconductor device according to claim 1 , further comprising a first electrically isolated conductor pattern,
wherein the first insulating film includes a torus-like area which fully surrounds the first electrically isolated conductor pattern.