Resistive random-access memory with implanted and radiated channels
Resistive RAM (RRAM) devices having increased uniformity and related manufacturing methods are described. Greater uniformity of performance across an entire chip that includes larger numbers of RRAM cells can be achieved by uniformly creating enhanced channels in the switching layers through the use of radiation damage. The radiation, according to various described embodiments, can be in the form of ions, electromagnetic photons, neutral particles, electrons, and ultrasound.
1. A resistive random-access memory device comprising:
a first electrode;
a second electrode; and
a switching region that is between the first and second electrodes and comprises one or more enhanced mobility pathway structures that have been formed in a process of fabricating the device and extend at respective locations in the switching region;
wherein said enhanced mobility pathway structures:
are configured to provide enhanced mobility of charged species;
have respective electrical resistances that vary with a switching voltage applied between the first and second electrodes; and
comprise damage in the switching region caused by ion implantation at least a substantial portion of which has passed through the switching region and has been deposited outside the switching region.
2. The resistive memory device of claim 1 wherein said enhanced mobility pathway structures are formed absent an application of a voltage across to the switching region equal to or greater than a breakdown voltage.
3. The resistive memory device of claim 1 including a substrate, wherein said first electrode is a bottom electrode disposed above the substrate and below the switching region and said second electrode is a top electrode disposed above the switching region.
4. The resistive memory device of claim 3 wherein a majority of ions used in said ion implantation are deposited below the switching region.
5. The resistive memory device of claim 4 wherein a majority of ions used in said ion implantation are deposited below the bottom electrode.
6. The resistive memory device of claim 3 wherein at least some of the damage is due to collision events caused by the ion implantation, and the majority of the collision events occur below the switching region.
7. The resistive memory device of claim 3 wherein a predominant peak in a distribution profile of ions used implanted in said ion implantation is below the switching region.
8. The resistive memory device of claim 3 wherein said ion implantation causes substantial collision events throughout a thickness of the switching region.
9. The resistive memory device of claim 1 including a barrier layer between the switching layer and the first electrode, which barrier layer is functionally disrupted by the ion implantation.
10. The resistive memory device of claim 1 including a barrier layer between the switching region and the second electrode, which barrier layer is functionally disrupted by the ion implantation.
11. The resistive memory device of claim 1 wherein said ion implantation is through the first and second electrodes.
12. The resistive memory device of claim 11 wherein said second electrode, which is above the switching region, comprises a first portion through which said ion implantation takes place and a thickening portion formed subsequently.
13. The resistive memory device of claim 1 including an underlying substrate having a primary planar upper surface, wherein a first planar interface between the first electrode and the switching region and a second planar interface between the switching region and the second electrode are non-parallel with the primary planar upper surface of the underlying substrate.
14. The resistive memory device of claim 13 wherein the first and second planar interfaces are approximately normal to the primary planar upper surface of the underlying substrate.
15. The resistive memory device of claim 14 wherein in said ion implantation the ions are implanted primarily in a direction that is normal to the primary planar upper surface of the underlying substrate.
16. The resistive memory device of claim 15 comprising defects in the switching region caused by said ion implantation, which defects are approximately uniformly distributed across a plane normal to the first and second planar interfaces.
17. The resistive memory device of claim 14 wherein the ion implantation is primarily in a direction that is at an acute angle to the primary planar upper surface of the underlying substrate.
18. The resistive memory device of claim 13 including at least one of (i) a barrier layer formed between the switching region and the first electrode and functionally disrupted by said ion implantation and (ii) a barrier layer formed between the switching region and the second electrode and functionally disrupted by said ion implantation.
19. The resistive memory device of claim 1 wherein the switching region is formed of a transition metal oxide material.
20. The resistive memory device of claim 1 wherein the implanted ions are selected from a group consisting of: Ag, Ti, Ta, Hf, O, Au, Fe, Ni, Ti, Ta, V, Pb, Bi, W, H, Ar, C, Si, B, P, Ga, As, Te, Al, Zn, In, and Sn.
21. The resistive memory device of claim 1 wherein the switching region is formed in situ by said ion implantation.
22. The resistive memory device of claim 21 wherein the implantation includes implanting oxygen ions into the switching region, wherein the switching region is initially formed of one or more transition metal materials.
23. The resistive memory device of claim 1 wherein the switching region has a built-in stress and the ion implantation increases the stress in the switching region and facilitates creation of said enhanced mobility pathway structures.
24. The resistive memory device of claim 23 wherein the switching region comprises at least one of large atomic mass atoms and mismatched material layers causing said built-in stress.
25. The resistive memory device of claim 1 in which the enhanced mobility pathway structures are formed at least in part by collision events in said ion implantation, which collision events are distributed substantially uniformly throughout the switching region.
26. A method of fabricating a resistive random-access memory device comprising:
forming a first electrode;
forming a switching layer;
forming a second electrode such that the switching layer is between the first and second electrodes; and
carrying out ion implantation in which a portion of the ions both enter and exit the switching layer and thereby facilitate forming, in the process of fabricating the device, one or more enhanced mobility pathways structures that provide enhanced mobility of charged species such that resistance between said first and second electrodes through the switching layer can be increased and decreased by applying a switching voltage between the first and second electrodes.
27. The method of claim 26 wherein the forming of one or more enhanced mobility pathway structures is due to the ion implantation rather than an application of a voltage to the switching layer equal to or greater than a breakdown voltage for the switching layer.
28. The method of claim 26 wherein said first electrode is a bottom electrode that is above a substrate and below the switching layer and said second electrode is a top electrode that is above the switching layer.
29. The method of claim 28 wherein a majority of the ions entering the switching layer in said ion implantation exit the switching layer.
30. The method of claim 28 wherein the ion implantation causes collision events and the majority of the collision events occurs in locations below the switching layer.
31. The method of claim 26 wherein the ion implantation functionally disrupts at least one of a barrier layer formed between the switching layer and the first electrode and a barrier layer formed between the switching layer and the second electrode.
32. The method of claim 26 wherein a first planar interface between the first electrode and the switching layer and a second planar interface between the switching layer and the second electrode are approximately normal with a primary planar upper surface of an underlying substrate.
33. The method of claim 32 wherein the implanting of ions is primarily in a direction that is normal to the primary planar upper surface of the underlying substrate.
34. The method of claim 26 wherein the implanting of ions comprises traversing one of the electrodes with the ions before the ions reach the switching layer.
35. A method of fabricating a resistive random-access memory device comprising:
forming a first electrode;
forming a switching region;
forming a second electrode such that the switching region is positioned between the first and second electrodes; and
damaging the switching region by directing energy into and past the switching region in the course of fabricating the device thereby facilitating forming one or more enhanced mobility pathways structures that provide enhanced mobility of charged species such that resistance between said first and second electrodes through the switching layer can be increased and decreased by applying a switching voltage between the first and second electrodes.
36. The method of claim 35 wherein the directed energy is in the form of one or more of ions, electrons, X-rays, gamma rays, light including UV and IR light, and ultrasound.
37. The method of claim 36 wherein the damaging causes collision events and the majority of the collision events occurs in locations other than the switching region.
38. The method of claim 35 wherein the directed energy passes through at least a portion of the first and a portion of the second electrodes.
39. The method of claim 38 wherein the directed energy functionally disrupts at least one of a barrier layer formed between the switching region and the first electrode and a barrier layer formed between the switching region and the second electrode.
40. A resistive random-access memory device comprising:
a first electrode;
a second electrode; and
a switching region that is between the first and second electrodes and comprises a multiplicity of enhanced mobility pathway structures that extend at respective locations in the switching region and are configured to provide enhanced mobility of charged species and have respective electrical resistances that vary with a switching voltage applied between the first and second electrodes across the pathway structures;
wherein said enhanced mobility pathway structures comprise damage in the switching region caused by directed energy beamed into, passing through, and extending beyond the switching region.
41. The resistive memory device of claim 40 wherein the enhanced mobility pathway structures comprise damage in the switching region caused by directed energy in the form of one or more of ions, electrons, X-rays, gamma rays, light including UV and IR light, and ultrasound.
42. The resistive memory device of claim 40 wherein the enhanced mobility pathway structures comprise damage in the switching region caused by ion implantation into the switching region.
43. The resistive memory device of claim 40 wherein the enhanced mobility pathway structures comprise damage in the switching region caused by directed energy in the form of at least one of X-rays, gamma rays, and electrons.
44. The resistive memory device of claim 40 wherein the enhanced mobility pathway structures comprise damage in the switching region caused by directed energy in the form of radiation having wavelengths longer than of X-rays.
45. A resistive random-access memory device comprising:
a stack of first electrodes;
a stack of second electrodes; and
a stack of switching regions each of which is between a respective pair of one of the first electrodes and one of the second electrodes;
wherein each of the switching regions comprises one or more enhanced mobility pathway structures configured to provide enhanced mobility of charged species and having respective electrical resistances that vary with a switching voltage applied across the pathway structures; and
wherein said enhanced mobility pathway structures comprise damage in the switching regions caused by directed energy concurrently beamed into and through the switching regions in the stack thereof.
46. The resistive memory device of claim 45 in which said damage caused by the directed energy is caused by directed energy in the form of ion implantation.
47. The resistive memory device of claim 45 in which said damage caused by the directed energy is caused by directed energy in the form of radiation in the energy range of 1-100 KeV.
48. The resistive memory device of claim 45 in which the stack of switching region comprises 2-20 switching regions.
49. The resistive memory device of claim 45 including an array of laterally spaced stacks each comprising first and second electrodes and switching regions, wherein the laterally spaced stacks are interconnected by electrical lines and form an integrated memory structure.
50. The resistive memory of claim 45 in which the switching regions are stacked in the direction in which the directed energy is beamed.