Issuing instructions to multiple execution units
A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.
1. A method for operating a microprocessor having a plurality of execution units arranged in an array, the method comprising:
receiving a group of instructions of an instruction stream from an instruction fetch unit, a target selector unit pointing to a row of available execution units within the array for instruction issue;
issuing the instructions from the instruction stream to the row of available execution units within the array;
moving the target selector unit to a next row of available execution units within the array; and
repeating the receiving, issuing, and moving with a next group of instructions of the instruction stream.
2. The method of claim 1 , wherein a plurality of instructions of the instruction stream are received from the instruction fetch unit, wherein prior to issuing the instructions, at least some of the plurality of instructions are rearranged by an optimizer unit based on rearranging portions of loop graphs to provide a new arrangement of rearranged instructions, and wherein the issuing of the instructions includes issuing the rearranged instructions in order of the new arrangement.
3. The method of claim 2 , wherein the rearranging of the instructions by an optimizer unit includes partitioning loop code.
4. The method of claim 1 , wherein the instruction stream is generated by a high level language compiler, the compiler arranging the instructions of the instruction stream in an optimized order for issuing to the execution units.
5. The method of claim 4 , wherein the arranging of the instructions by the compiler includes partitioning loop code.
6. The method of claim 1 , further comprising providing, by a plurality of groups of one or more execution units, status information indicating the availability of the one or more execution units to a target selector unit,
wherein the target selector unit points to the available execution unit for instruction issue in response to the status information.
7. A method for operating a microprocessor having a plurality of execution units, the method comprising:
providing, by a plurality of groups of one or more execution units, status information indicating the availability of the one or more execution units to a target selector unit;
receiving an instruction of an instruction stream from an instruction fetch unit, the target selector unit pointing to an available execution unit for instruction issue in response to the status information;
issuing the instruction from the instruction stream to the available execution unit;
moving the target selector unit to a next available execution unit; and
repeating the receiving, issuing, and moving with a next instruction of the instruction stream.
8. The method of claim 7 wherein the plurality of execution units are arranged in an array,
wherein receiving an instruction includes receiving a group of instructions of the instruction stream from the instruction fetch unit, wherein the target selector unit points to a row of available execution units within the array for instruction issue,
wherein issuing the instruction includes issuing the group of instructions from the instruction stream to the row of available execution units within the array,
wherein moving the target selector unit to a next available execution unit includes moving the target selector unit to a next row of available execution units within the array, and
wherein repeating the receiving, issuing, and moving with a next instruction includes repeating the receiving, issuing, and moving with a next group of instructions of the instruction stream.
9. The method of claim 7 , wherein a plurality of instructions of the instruction stream are received from the instruction fetch unit, wherein prior to issuing the instructions, at least some of the plurality of instructions are rearranged by an optimizer unit based on rearranging portions of loop graphs to provide a new arrangement of rearranged instructions, and wherein the issuing of the instructions includes issuing the rearranged instructions in order of the new arrangement.
10. The method of claim 9 , wherein the rearranging of the instructions by an optimizer unit includes partitioning loop code.
11. The method of claim 7 , wherein the instruction stream is generated by a high level language compiler, the compiler arranging the instructions of the instruction stream in an optimized order for issuing to the execution units.
12. The method of claim 11 , wherein the arranging of the instructions by the compiler includes partitioning loop code.