Power semiconductor device with over-current protection
View Patent ↗A power semiconductor device has an upper transistor and a lower transistor that is coupled in cascode with the upper transistor. The upper transistor comprises an upper drain, upper gate, and an upper source. The lower transistor comprises a lower drain that is coupled to the upper source, a lower gate, and a lower source that is coupled to the upper gate. The upper transistor is a depletion mode device and has a first saturation current. The lower transistor is an enhancement mode device and has a second saturation current, which is lower than the first saturation current.
1. A power semiconductor device comprising:
an upper high electron mobility transistor (HEMT) comprising an upper drain, an upper gate, and an upper source;
a lower metal oxide semiconductor field effect transistor (MOSFET) coupled in cascode with the upper HEMT and comprising a lower drain that is coupled to the upper source, a lower gate, and a lower source that is coupled to the upper gate, wherein:
the upper HEMT is a depletion mode device and has a first saturation current;
the lower MOSFET transistor is an enhancement mode device and has a second saturation current; and
the second saturation current is less than or equal to 70% of the first saturation current.
2. The power semiconductor device of claim 1 wherein the upper HEMT is a gallium nitride (GaN) HEMT.
3. The power semiconductor device of claim 2 wherein the lower MOSFET is a silicon (Si) MOSFET.
4. The power semiconductor device of claim 1 wherein the second saturation current is less than or equal to 50% of the first saturation current.
5. The power semiconductor device of claim 1 wherein the second saturation current is less than or equal to 30% of the first saturation current.
6. The power semiconductor device of claim 1 wherein the upper HEMT has a reverse breakdown voltage that is greater than or equal to 5 times a reverse breakdown voltage of the lower MOSFET.
7. The power semiconductor device of claim 1 wherein the upper HEMT has a reverse breakdown voltage that is greater than or equal to 10 times a reverse breakdown voltage of the lower MOSFET.
8. The power semiconductor device of claim 7 wherein the reverse breakdown voltage of the upper HEMT is at least 400 volts.
9. The power semiconductor device of claim 1 wherein the second saturation current is less than or equal to 50% of the first saturation current, and the upper HEMT has a reverse breakdown voltage that is greater than or equal to 10 times a reverse breakdown voltage of the lower MOSFET.
10. The power semiconductor device of claim 1 wherein the upper HEMT is formed from a first semiconductor material system, and the lower MOSFET is formed from a second semiconductor material system, which is different from the first semiconductor material system.
11. The power semiconductor device of claim 8 wherein the upper HEMT is a gallium nitride (GaN) HEMT, and the lower MOSFET is a silicon (Si) MOSFET.
12. The power semiconductor device of claim 8 wherein the second saturation current is less than or equal to 50% of the first saturation current.
13. The power semiconductor device of claim 8 wherein the second saturation current is less than or equal to 30% of the first saturation current.
14. The power semiconductor device of claim 1 wherein:
the second saturation current is less than or equal to 30% of the first saturation current;
the upper transistor has a reverse breakdown voltage that is greater than or equal to 5 times a reverse breakdown voltage of the lower transistor; and
the reverse breakdown voltage of the upper transistor is at least 400 volts.
15. The power semiconductor device of claim 14 wherein the upper HEMT is a gallium nitride (GaN) HEMT, and the lower MOSFET is a silicon (Si) MOSFET.