POWER TRANSISTOR WITH DISTRIBUTED DIODES
An electronic circuit is disclosed. The electronic circuit includes a distributed power switch. In some embodiments, the electronic circuit also includes one or more of a distributed gate driver, a distributed gate pulldown device, a distributed diode, and a low resistance gate and/or source connection structure. An electronic component comprising the circuit, and methods of manufacturing the circuit are also disclosed.
1 . An electronic circuit, comprising:
a substrate comprising GaN;
a distributed power switch formed on the substrate, wherein the distributed power switch comprises a plurality of power sub-transistors, and wherein each power sub-transistor comprises a gate, a source, and a drain; and
a distributed diode formed on the substrate, wherein the distributed diode comprises a plurality of sub-diodes, wherein each sub-diode comprises an anode, and a cathode, wherein the anodes of the sub-diodes are each connected to a source of one or more corresponding power sub-transistors, and wherein the cathodes of the sub-diodes are each connected to a drain of one or more corresponding power sub-transistors.
2 . The electronic circuit of claim 1 , wherein the distributed diode is formed by electrically connecting a gate and a source of each of a plurality of sub-transistors of the distributed power switch with a conductor.
3 . The electronic circuit of claim 1 , wherein the distributed diode is formed by electrically connecting a source electrode of at least two of the sub-transistors of the distributed power switch to the substrate with a Schottky metal.
4 . The electronic circuit of claim 1 , further comprising a distributed drive circuit formed on the substrate, wherein the distributed drive circuit comprises a distributed output stage formed by a plurality of sub-drivers, wherein each sub-driver comprises an input and an output, and wherein the output of each sub-driver is connected to a gate of one or more corresponding sub-transistors of the sub-transistors of the distributed power switch.
5 . The electronic circuit of claim 4 , further comprising a distributed pulldown transistor formed on the substrate, wherein the distributed pulldown transistor comprises a plurality of pulldown sub-transistors, wherein each pulldown sub-transistor comprises a gate, a source, and a drain, wherein the gates of the pulldown sub-transistors are electrically connected together, wherein the sources of the pulldown sub-transistors are each connected to a source of one or more corresponding power sub-transistors, and wherein the drains of the pulldown sub-transistors are each connected to a gate of the corresponding power sub-transistors.
6 . The electronic circuit of claim 5 , further comprising:
a first conductor connected to the gates of the power sub-transistors;
a second conductor connected to the sources of the power sub-transistors;
a third conductor overlapping at least a portion of the second conductor, wherein the third conductor comprises:
a first portion connected to the second conductor with one or more vias, and
a second portion connected to the first conductor with one or more vias; and
a fourth conductor overlapping the second portion of the third conductor, and connected to the first conductor by the second portion of the third conductor, wherein the fourth conductor has a thickness of at least 2 microns.
7 . The electronic circuit of claim 4 , further comprising:
a first conductor connected to the gates of the power sub-transistors;
a second conductor connected to the sources of the power sub-transistors;
a third conductor overlapping at least a portion of the second conductor, wherein the third conductor comprises:
a first portion connected to the second conductor with one or more vias, and
a second portion connected to the first conductor with one or more vias; and
a fourth conductor overlapping the second portion of the third conductor, and connected to the first conductor by the second portion of the third conductor, wherein the fourth conductor has a thickness of at least 2 microns.
8 . The electronic circuit of claim 1 , further comprising a distributed pulldown transistor formed on the substrate, wherein the distributed pulldown transistor comprises a plurality of pulldown sub-transistors, wherein each pulldown sub-transistor comprises a gate, a source, and a drain, wherein the gates of the pulldown sub-transistors are electrically connected together, wherein the sources of the pulldown sub-transistors are each connected to a source of one or more corresponding power sub-transistors, and wherein the drains of the pulldown sub-transistors are each connected to a gate of the corresponding power sub-transistors.
9 . The electronic circuit of claim 8 , further comprising:
a first conductor connected to the gates of the power sub-transistors;
a second conductor connected to the sources of the power sub-transistors;
a third conductor overlapping at least a portion of the second conductor, wherein the third conductor comprises:
a first portion connected to the second conductor with one or more vias, and
a second portion connected to the first conductor with one or more vias; and
a fourth conductor overlapping the second portion of the third conductor, and connected to the first conductor by the second portion of the third conductor, wherein the fourth conductor has a thickness of at least 2 microns.
10 . The electronic circuit of claim 1 , further comprising:
a first conductor connected to the gates of the power sub-transistors;
a second conductor connected to the sources of the power sub-transistors;
a third conductor overlapping at least a portion of the second conductor, wherein the third conductor comprises:
a first portion connected to the second conductor with one or more vias, and
a second portion connected to the first conductor with one or more vias; and
a fourth conductor overlapping the second portion of the third conductor, and connected to the first conductor by the second portion of the third conductor, wherein the fourth conductor has a thickness of at least 2 microns.
11 . An electronic component, comprising:
a package base; and
at least one GaN-based die secured to the package base and including an electronic circuit comprising:
a substrate comprising GaN;
a distributed power switch formed on the substrate, wherein the distributed power switch comprises a plurality of power sub-transistors, and wherein each power sub-transistor comprises a gate, a source, and a drain; and
a distributed diode formed on the substrate, wherein the distributed diode comprises a plurality of sub-diodes, wherein each sub-diode comprises an anode, and a cathode, wherein the anodes of the sub-diodes are each connected to a source of one or more corresponding power sub-transistors, and wherein the cathodes of the sub-diodes are each connected to a drain of one or more corresponding power sub-transistors.
12 . The electronic component of claim 11 , wherein the distributed diode is formed by electrically connecting a gate and a source of each of a plurality of sub-transistors of the distributed power switch with a conductor.
13 . The electronic component of claim 11 , wherein the distributed diode is formed by electrically connecting a source electrode of at least two of the sub-transistors of the distributed power switch to the substrate with a Schottky metal.
14 . The electronic component of claim 11 , wherein the electronic circuit further comprises a distributed drive circuit formed on the substrate, wherein the distributed drive circuit comprises a distributed output stage formed by a plurality of sub-drivers, wherein each sub-driver comprises an input and an output, and wherein the output of each sub-driver is connected to a gate of one or more corresponding sub-transistors of the sub-transistors of the distributed power switch.
15 . The electronic component of claim 14 , wherein the electronic circuit further comprises a distributed pulldown transistor formed on the substrate, wherein the distributed pulldown transistor comprises a plurality of pulldown sub-transistors, wherein each pulldown sub-transistor comprises a gate, a source, and a drain, wherein the gates of the pulldown sub-transistors are electrically connected together, wherein the sources of the pulldown sub-transistors are each connected to a source of one or more corresponding power sub-transistors, and wherein the drains of the pulldown sub-transistors are each connected to a gate of the corresponding power sub-transistors.
16 . The electronic component of claim 15 , wherein the electronic circuit further comprises:
a first conductor connected to the gates of the power sub-transistors;
a second conductor connected to the sources of the power sub-transistors;
a third conductor overlapping at least a portion of the second conductor, wherein the third conductor comprises:
a first portion connected to the second conductor with one or more vias, and
a second portion connected to the first conductor with one or more vias; and
a fourth conductor overlapping the second portion of the third conductor, and connected to the first conductor by the second portion of the third conductor, wherein the fourth conductor has a thickness of at least 2 microns.
17 . The electronic component of claim 14 , wherein the electronic circuit further comprises:
a first conductor connected to the gates of the power sub-transistors;
a second conductor connected to the sources of the power sub-transistors;
a third conductor overlapping at least a portion of the second conductor, wherein the third conductor comprises:
a first portion connected to the second conductor with one or more vias, and
a second portion connected to the first conductor with one or more vias; and
a fourth conductor overlapping the second portion of the third conductor, and connected to the first conductor by the second portion of the third conductor, wherein the fourth conductor has a thickness of at least 2 microns.
18 . The electronic component of claim 11 , wherein the electronic circuit further comprises a distributed pulldown transistor formed on the substrate, wherein the distributed pulldown transistor comprises a plurality of pulldown sub-transistors, wherein each pulldown sub-transistor comprises a gate, a source, and a drain, wherein the gates of the pulldown sub-transistors are electrically connected together, wherein the sources of the pulldown sub-transistors are each connected to a source of one or more corresponding power sub-transistors, and wherein the drains of the pulldown sub-transistors are each connected to a gate of the corresponding power sub-transistors.
19 . The electronic component of claim 18 , wherein the electronic circuit further comprises:
a first conductor connected to the gates of the power sub-transistors;
a second conductor connected to the sources of the power sub-transistors;
a third conductor overlapping at least a portion of the second conductor, wherein the third conductor comprises:
a first portion connected to the second conductor with one or more vias, and
a second portion connected to the first conductor with one or more vias; and
a fourth conductor overlapping the second portion of the third conductor, and connected to the first conductor by the second portion of the third conductor, wherein the fourth conductor has a thickness of at least 2 microns.
20 . The electronic component of claim 11 , wherein the electronic circuit further comprises
a first conductor connected to the gates of the power sub-transistors;
a second conductor connected to the sources of the power sub-transistors;
a third conductor overlapping at least a portion of the second conductor, wherein the third conductor comprises:
a first portion connected to the second conductor with one or more vias, and
a second portion connected to the first conductor with one or more vias; and
a fourth conductor overlapping the second portion of the third conductor, and connected to the first conductor by the second portion of the third conductor, wherein the fourth conductor has a thickness of at least 2 microns.