IP Library Patent Application 14832094
Patent Application
App. No. 14/832,094

SINGLE CARRIER COMMUNICATIONS HARNESSING NONLINEARITY

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Quick Facts
Patent No.
US None
App. No.
14/832,094
Abstract

A single-carrier receiver comprises a (FEC) decoder and a nonlinearity compensation circuit. The nonlinearity compensation circuit is operable to generate estimates of constellation points transmitted on a received signal based on soft decisions from the FEC decoder and based on a model of nonlinear distortion introduced by a transmitter from which the received signal was received. The generation of the estimates may be based on a measure of distance between a function of the received signal and a synthesized version of the received signal. The generation of the estimates may comprise iterative processing of symbols of the received signal, and the iterative processing may comprise a plurality of outer iterations and a plurality of inner iterations.

Claims (41)

1 . A System comprising:

an single carrier receiver comprising a forward error correction (FEC) decoder and a nonlinearity compensation circuit, wherein:

said nonlinearity compensation circuit is operable to generate estimates of constellation points transmitted on a received signal; and

said generation of said estimates is based on:

soft decisions from said FEC decoder; and

a model of nonlinear distortion introduced by a transmitter from which said received signal was received.

2 . The system of claim 1 , wherein said generation of said estimates is based on a measure of distance that is either: between a function of said received signal and a synthesized version of said received signal, or between said estimates and decoder soft values.

3 . The system of claim 1 , wherein:

said generation of said estimates comprises iterative processing of symbols of said received signal; and

said iterative processing comprises a plurality of outer iterations and a plurality of inner iterations.

4 . The system of claim 3 , wherein:

said estimates are an output of said nonlinearity compensation circuit during a first particular outer iteration; and

said soft decisions are an output of said FEC decoder during a second particular outer iteration preceding said first particular outer iteration.

5 . The system of claim 3 , wherein:

said estimates are an output of said nonlinearity compensation circuit during a first particular outer iteration; and

for each of said inner iterations for said particular outer iteration, said FEC decoder generates variable-node-to-check-node messages based on said estimates.

6 . The system of claim 3 , wherein:

for a first one of said inner iterations for a first particular one of said outer iterations, said FEC decoder generates variable-node-to-check-node messages based on check-node-to-variable-node messages generated during a last one of said inner iterations for a second particular one of said outer iterations.

7 . The system of claim 6 , wherein, for said second particular one of said outer iterations, said inner iterations are halted before said FEC decoder converges.

8 . The system of claim 3 , wherein:

for a particular one of said outer iterations, said soft decisions from a previous one of said outer iterations are categorized and adjusted based on a category into which they are placed, said adjustment resulting in adjusted soft decisions; and

said estimates for said particular one of said iterations are generated based on said adjusted soft decisions.

9 . The system of claim 3 , wherein:

for a particular one of said outer iterations, an expectation is calculated using said soft decisions from a previous one of said outer iterations; and

said generation of said estimates is based on said expectation.

10 . The system of claim 3 , wherein said nonlinearity compensation circuitry is operable to:

during each successive outer iteration, refine one or more of said estimates generated during a previous outer iteration based on said soft decisions output by said FEC decoder during said previous outer iteration.

11 . The system of claim 10 , wherein:

said refinement is limited by one or more constraints; and

said constraints are determined based on said soft decisions.

12 . The system of claim 11 , wherein said constraints are updated for each successive one of said outer iterations.

13 . The system of claim 10 , wherein said generation of said estimates of said transmitted constellation points is based on a metric of distance between symbol estimation and said expectation, and said metric is affected from soft reliability measures.

14 . The system of claim 1 , wherein:

said nonlinearity compensation circuit is operable to generate said model based on a training sequence transmitted by said transmitter; and

said training sequence has a peak to average power ratio that causes an output of said power amplifier of said transmitter to compress and introduce nonlinear distortion.

15 . The system of claim 14 , wherein said training sequence comprises multiple permutations of a determined sequence of symbols.

16 . The system of claim 1 , wherein, for processing a particular received symbol, said nonlinearity compensation circuit is operable to determine said model of nonlinear distortion based on a first training sequence that preceded said particular received symbol and a second training sequence that followed said particular received symbol.

17 . The system of claim 16 , wherein said nonlinearity compensation circuitry is operable to use said first training sequence and said second training sequence to estimate phase noise present in said received signal.

18 . The system of claim 1 , wherein each of said soft decisions corresponds to only one of: a real dimension of said received signal and an imaginary dimension of said received signal.

19 . The system of claim 1 , wherein said estimate of nonlinear distortion introduced by said transmitter accounts for a digital nonlinear function implemented in said transmitter.

20 . The system of claim 19 , wherein said digital nonlinear function is a protective clip.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2017
From: MAGNACOM LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041604/0861 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 28, 2015
From: BENJO, SHIMON; CHAIKIN, SHLOMY; ELIAZ, AMIR; INTRATER, AMOS; OREN, ROY; PITARASHO, GAL; REUVEN, ILAN; STOPLER, DANIEL
To: MAGNACOM LTD.
Reel/Frame 036898/0029 →