Reducing wafer warpage during wafer processing
View Patent ↗A manufacturing method of a semiconductor device that can reduce warpage during wafer processing. The method includes forming a first guard ring around a first chip region on a semiconductor wafer. The method includes forming a second guard ring around a second chip region on the semiconductor wafer. The method includes mechanically connecting the first guard ring with the second guard ring through a joist structure.
1. A semiconductor wafer comprising:
a first guard ring surrounding a first chip region at a planar view;
a second guard ring surrounding a second chip region at a planar view; and
a joist structure mechanically connecting the first guard ring with the second guard ring,
wherein the joist structure includes a number of connection patterns connecting a first portion with a second portion, the first portion being a portion extending along the second guard ring in the first guard ring, the second portion being a portion extending along the first guard ring in the second guard ring, and
wherein a number of the connection patterns extend between the first portion and the second portion not to overlap a mark pattern arranged between the first portion and the second portion.
2. A semiconductor wafer comprising:
a first guard ring surrounding a first chip region at a planar view;
a second guard ring surrounding a second chip region at a planar view; and
a joist structure mechanically connecting the first guard ring with the second guard ring,
wherein the joist structure includes a number of connection patterns connecting a first portion with a second portion, the first portion being a portion extending along the second guard ring in the first guard ring, the second portion being a portion extending along the first guard ring in the second guard ring, and
wherein a number of the connection patterns include
a first connection pattern connecting one end side of the first portion with one end side of the second portion,
a second connection pattern connecting another end side of the first portion with another end side of the second portion, and
a third connection pattern connecting the first portion with the second portion between the first connection pattern and the second connection pattern.
3. The semiconductor wafer according to claim 2 ,
wherein each of the first connection pattern, the second connection pattern, and the third connection pattern extends obliquely to a longitudinal direction of the first portion.
4. The semiconductor wafer according to claim 2 ,
wherein a number of the connection patterns further include
a fourth connection pattern extending to intersect with the first connection pattern and connecting one end side of the first portion with one end side of the second portion,
a fifth connection pattern extending to intersect with the second connection pattern and connecting another end side of the first portion with another end side of the second portion, and
a sixth connection pattern extending to intersect with the third connection pattern and connecting the first portion with the second portion between the first connection pattern and the second connection pattern.
5. The semiconductor wafer according to claim 4 ,
wherein the first connection pattern and the fourth connection pattern form substantially a letter X shape at a planar view,
the second connection pattern and the fifth connection pattern form substantially a letter X shape at a planar view, and
the third connection pattern and the sixth connection pattern form substantially a letter X shape at a planar view.
6. The semiconductor wafer according to claim 2 ,
wherein an interval between the first connection pattern and the third connection pattern in a longitudinal direction of the first portion is equivalent to an interval between the third connection pattern and the second connection pattern in the longitudinal direction of the first portion.