Memory system and information processing system
View Patent ↗A memory system includes a controller configured to write data to a nonvolatile memory. The controller includes a buffer unit configured to hold write data including a plurality of pieces of unit data, a sequencer configured to receive the write data from the buffer unit and individually output the plurality of pieces of unit data sequentially, and a plurality of cores, each being configured to encrypt at least one of the pieces of unit data output from the sequencer. The buffer is further configured to output the plurality of pieces of unit data sequentially to the sequencer, such that a last piece of unit data is output consecutively after a preceding piece of unit data is output.
1. A controller for a memory system, the controller comprising:
a host interface through which a write command and first write data associated with the write command are received; and
an encryption unit configured to perform encryption of the first write data, the encryption unit including
a buffer configured to store the first write data;
a sequencer configured to read the first write data from the buffer and output the first write data as a plurality of sequential pieces of unit data;
a plurality of first cores, each being configured to encrypt at least one of the pieces of unit data output from the sequencer;
a checker configured to receive from the sequencer a request to search a key identification code for the first write data;
a search unit configured to search for an encryption key corresponding to the key identification code; and
a second core including a key expansion unit configured to expand the encryption key, and a core encryption unit configured to encrypt an initialization vector using the expanded encryption key and output the encrypted initialization vector to each of the first cores.
2. The controller according to claim 1 , wherein
one of the first cores encrypts both the last piece of unit data and the preceding piece of unit data.
3. The controller according to claim 1 , wherein
the buffer is further configured to output a header to the sequencer prior to outputting the first write data to the sequencer.
4. The controller according to claim 1 , wherein
the search unit stores correspondence between the key identification code and the encryption key.
5. The systcm controller according to claim 1 , wherein
each of the first cores encrypts the piece of unit data using the encrypted initialization vector output from the second core.
6. The controller according to claim 1 , wherein
the checker is further configured to receive from the sequencer a second request to search a second key identification code for second write data stored in the buffer after the first write data,
the search unit is further configured to search for a second encryption key corresponding to the second key identification code, and
the key expansion unit is further configured to expand the second encryption key while one of the first cores encrypts a piece of unit data.
7. The controller according to claim 1 , wherein
the sequencer is further configured to read second write data from the buffer after reading the first write data, and includes a counter configured to count the number of pieces of unit data in the write data read from the buffer, and calculate a sum of the number of pieces of unit data in the first write data and the number of pieces of unit data in the second write data.
8. The controller according to claim 1 , wherein
the sequencer is further configured to read second write data from the buffer, after reading the first write data, and output the second write data as a plurality of sequential pieces of unit data to the plurality of first cores, and
a first piece of unit data in the second write data is output to one of the first cores that is configured to receive a piece of unit data that is immediately subsequent to a piece of unit data received by another one of the cores that receives the last piece of unit data in the first write data.
9. The controller according to claim 1 , further comprising:
a second sequencer configured to receive the encrypted pieces of unit data from the plurality of first cores; and
a writing unit configured to write the encrypted pieces of unit data in the nonvolatile memory.
10. An information processing system, comprising:
a host configured to transmit first write data;
a nonvolatile memory; and
a controller configured to receive the first write data from the host and write the first write data to the nonvolatile memory, wherein
the controller includes:
a buffer configured to store the first write data;
a sequencer configured to read the first write data from the buffer and output the first write data as a plurality of sequential pieces of unit data;
a plurality of first cores, each being configured to encrypt at least one of the pieces of unit data output from the sequencer;
a checker configured to receive from the sequencer a request to search a key identification code for the first write data;
a search unit configured to search for an encryption key corresponding to the key identification code; and
a second core including a key expansion unit configured to expand the encryption key, and a core encryption unit configured to encrypt an initialization vector using the expanded encryption key and output the encrypted initialization vector to each of the first cores.
11. The information processing system according to claim 10 , wherein
one of the first cores encrypts both the last piece of unit data and the preceding piece of unit data.
12. The information processing system according to claim 10 , wherein
the buffer is further configured to output a header to the sequencer prior to outputting the first write data.
13. The information processing system according to claim 10 , wherein
the checker is further configured to receive from the sequencer a second request to search a second key identification code for second write data stored in the buffer after the first write data,
the search unit is further configured to search for a second encryption key corresponding to the second key identification code, and
the key expansion unit is further configured to expand the second encryption key while one of the first cores encrypts a piece of unit data.
14. The information processing system according to claim 10 , wherein
the sequencer is further configured to read second write data from the buffer after reading the first write data, and includes a counter configured to count the number of pieces of unit data in the write data read from the buffer, and calculate a sum of the number of pieces of unit data in the first write data and the number of pieces of unit data in the second write data.
15. The information processing system according to claim 10 , wherein
the sequencer is further configured to read second write data from the buffer, after receiving reading the first write data, and output the second write data as a plurality of sequential pieces of unit data to the plurality of first cores, and
a first piece of unit data in the second write data is output to one of the cores that is configured to receive a piece of unit data that is immediately subsequent to a piece of unit data received by another one of the cores that receives the last piece of unit data in the first write data.